Computational nodes fusion in a reconfigurable data processor

A system comprising:

• an array of reconfigurable units and a configuration module to provide configuration data to configure a plurality of configurable elements in the array of reconfigurable units such as pattern memory units (PMUs), pattern compute units (PCUs), and communication agents,
• a compiler configured to generate a pipeline of a plurality of PCUs related to a dataflow graph, interleaved between a plurality of PMUs, wherein
• each PCU is coupled to perform calculations based on data received from a first PMU of the plurality of PMUs and store results of the calculations into a second PMU of the plurality of PMUs after a latency, wherein the first PMU is placed before the PCU and the second PMU is after the PCU in the pipeline,
• and wherein the compiler is further configured to remove the first PMU or the second PMU from the pipeline based on a comparison of the latencies of the PCUs.