# US 2025/0098550 A1 · Quantum device and method of manufacturing same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2025/0098550 A1
- Document ID: US20250098550A1
- Status: Published application
- Kind: A1
- Application number: 18/670,767
- Filed: 2024-05-22
- Published: 2025-03-20
- Earliest claimed: 2023-09-20
- Assignees: NEC Corporation
- Applicants: NEC Corporation
- Inventors: Katsumi KIKUCHI; Satoshi TSUKIYAMA; Tomohiro NISHIYAMA
- Web page: https://patentgrep.com/patent/US20250098550A1

## CPC

- H10N 60/81: Containers; Mountings
- H10N 60/01: Manufacture or treatment
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A quantum device using a quantum state, including a quantum chip, a wiring component having a wiring layer, and a laminated substrate installed so that at least the surface of the wiring component on which the quantum chip is mounted is exposed, wherein a wiring layer of the laminated substrate and the wiring layer of the wiring component are connected by an integrated conductor pattern.

## Claims

### Claim 1

A quantum device using a quantum state, comprising:
a quantum chip;
a wiring component having a wiring layer;
a laminated substrate installed so that at least the surface of the wiring component on which the quantum chip is mounted is exposed; and
an integrated conductor pattern connecting the wiring layer of the laminated substrate with the wiring layer of the wiring component.

### Claim 2 (depends on 1)

The quantum device according to claim 1, wherein the wiring component is embedded in the laminated substrate.

### Claim 3 (depends on 2)

The quantum device according to claim 2, further comprising a relief portion at at least either one of an outer surface corner between one outer surface of the wiring component and another outer surface that intersects that one outer surface, and an inner surface corner between one inner surface of the laminated substrate and another inner surface that intersects that one inner surface.

### Claim 4 (depends on 1)

The quantum device according to claim 1, wherein the conductor pattern includes a portion of a conductor layer on the surface of the laminated substrate.

### Claim 5 (depends on 1)

The quantum device according to claim 1, further comprising the wiring component having a plurality of the wiring layers.

### Claim 6 (depends on 1)

The quantum device according to claim 1, wherein the wiring component includes a core material and a through-via that penetrates the core material.

### Claim 7 (depends on 1)

The quantum device according to claim 1, wherein the wiring component includes a plurality of divided wiring components arranged on the laminated substrate, and the quantum chip is arranged across the divided wiring components.

### Claim 8 (depends on 1)

The quantum device according to claim 1, wherein a plurality of the quantum chips are arranged on the single wiring component.

### Claim 9 (depends on 1)

The quantum device according to claim 1, wherein all or part of the quantum chip is arranged to overlap the wiring component in plan view.

### Claim 10 (depends on 1)

The quantum device according to claim 1, wherein the quantum chip is arranged so as to overlap a plurality of the wiring components in plan view.

### Claim 11 (depends on 1)

The quantum device according to claim 1, wherein the laminated substrate has a plurality of wiring layers.

### Claim 12 (depends on 1)

The quantum device according to claim 1, wherein an insulating layer of the laminated substrate is composed of organic materials.

### Claim 13 (depends on 1)

The quantum device according to claim 1, wherein the laminated substrate is provided with a connector.

### Claim 14 (depends on 13)

The quantum device according to claim 13, wherein the laminated substrate has a plurality of connectors, some of the connectors being connected to some circuits of the wiring component, and other connectors being connected to other circuits of the wiring component.

### Claim 15

A method of manufacturing a quantum device comprising a quantum chip, a wiring component having a wiring layer, and a laminated substrate installed so that at least the surface of the wiring component on which the quantum chip is mounted is exposed, the method comprising:
embedding the wiring component in a recess of the laminated substrate; and
connecting the laminated substrate and the wiring component by an integrated conductor pattern.