# US 2025/0098359 A1 · Silicon wafers having passivated contacts

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- Number: US 2025/0098359 A1
- Document ID: US20250098359A1
- Status: Published application
- Kind: A1
- Application number: 18/885,915
- Filed: 2024-09-16
- Published: 2025-03-20
- Earliest claimed: 2023-09-14
- Assignees: Alliance for Sustainable Energy, LLC; Colorado School of Mines; Universita' Degli Studi Di Padova
- Applicants: Alliance for Sustainable Energy, LLC; Colorado School of Mines; Università degli Studi di Padova
- Inventors: Pauls STRADINS; David Levi YOUNG; Kejun CHEN; Sumit AGARWAL; Enrico NAPOLITANI; William Michael NEMETH
- Web page: https://patentgrep.com/patent/US20250098359A1

## CPC

- H10F 71/129: {Passivating}
- H10F 71/121: {The active layers comprising only Group IV materials}
- H10F 71/128: {Annealing}
- H10F 71/134: {Irradiation with electromagnetic or particle radiation}
- H10F 77/703: {of the semiconductor bodies, e.g. textured active layers}
- H10F 10/165: the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION

## Abstract

The present disclosure relates to a wafer that includes a silicon core having a textured surface and a dielectric layer having a first thickness, where the textured surface includes a plurality of features where each feature is characterized by a first point and a second point separated by a distance, H, at least a portion of the features further include a solid channel positioned substantially at or near the first point, and the solid channel passes through at least a portion of the first thickness.

## Claims

### Claim 1

A wafer comprising:
a silicon core comprising a textured surface; and
a dielectric layer comprising a first thickness, wherein:
the textured surface comprises a plurality of features where each feature is characterized by a first point and a second point separated by a distance, H,
at least a portion of the features further comprise a solid channel positioned substantially at or near the first point, and
the solid channel passes through at least a portion of the first thickness.

### Claim 2 (depends on 1)

The wafer of claim 1, further comprising a silicon layer comprising a second thickness, wherein:
the dielectric layer is positioned between the silicon core and the silicon layer,
the silicon layer maintains the textured shape of the textured silicon core, and
the solid channel passes through at least one of a portion of the first thickness or a portion of the second thickness or a combination thereof.

### Claim 3 (depends on 2)

The wafer of claim 2, wherein the solid channel passes completely through each of the first thickness and the second thickness.

### Claim 4 (depends on 1)

The wafer of claim 1, wherein the dielectric layer comprises at least one of a silicon oxide, an aluminum oxide, or a silicon nitride, or a combination thereof.

### Claim 5 (depends on 1)

The wafer of claim 1, wherein H is between 100 nm and 10 μm.

### Claim 6 (depends on 1)

The wafer of claim 1, wherein the feature comprises at least one of a pyramid, a cone, a ridge, a circular bulge, an inverted pyramid, an inverted cone, a dimple, or a combination thereof.

### Claim 7 (depends on 6)

The wafer of claim 6, wherein the pyramid is characterized by:
a tip positioned at the first point,
a trough positioned at the second point,
at least three facets that meet to form the tip, and
the solid channel is positioned substantially at or near the tip.

### Claim 8 (depends on 1)

The wafer of claim 1, wherein the silicon core comprises at least one of a crystalline silicon or a multi-crystalline silicon or a combination thereof.

### Claim 9 (depends on 1)

The wafer of claim 1, wherein the first thickness is between 1.0 nm and 20 nm.

### Claim 10 (depends on 1)

The wafer of claim 1, wherein the second thickness is between 5 nm and 300 nm.

### Claim 11 (depends on 1)

The wafer of claim 1, wherein the solid channel has a diameter of less than 1000 nm

### Claim 12 (depends on 1)

The wafer of claim 1, further comprising a concentration of solid channels between 1×104 solid channels/cm2 and 1×1010 solid channels/cm2.

### Claim 13 (depends on 2)

The wafer of claim 2, further comprising a metal grid, wherein the silicon layer is positioned between the metal grid and the dielectric layer.

### Claim 14 (depends on 13)

The wafer of claim 13, wherein the solid channel is positioned under the metal grid.

### Claim 15 (depends on 2)

The wafer of claim 2, further comprising a sheet resistance, Rs, between 576Ω/□ and 719 Ω/□.

### Claim 16 (depends on 2)

The wafer of claim 2, further comprising an implied open-circuit voltage, iVoc, between 672 mV and 716 mV.

### Claim 17

A method comprising:
irradiating a wafer with a light, wherein:
the wafer comprises:
a silicon core comprising a textured surface;
a dielectric layer comprising a first thickness; and
a silicon layer comprising a second thickness, wherein;
the dielectric layer is positioned between the silicon core and the silicon layer;
the textured surface comprises a plurality of features where each feature is characterized by a first point and a second point separated by a distance, H, and the silicon layer maintains the textured shape of the textured silicon core; and
the irradiating creates a solid channel having a first diameter at the first point of at least a portion of the features.

### Claim 18 (depends on 17)

The method of claim 17, further comprising, after the irradiating, an etching of the wafer, wherein the etching increases a diameter of a solid channel.

### Claim 19 (depends on 17)

The method of claim 17, further comprising, before the irradiating, a pre-irradiating of the wafer with a second light, wherein in the pre-irradiating selectively weakens or thins the dielectric layer.