# US 2025/0098327 A1 · Integrated circuit based on grid and method of designing the same

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- Number: US 2025/0098327 A1
- Document ID: US20250098327A1
- Status: Published application
- Kind: A1
- Application number: 18/810,817
- Filed: 2024-08-21
- Published: 2025-03-20
- Earliest claimed: 2023-09-19
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Hankyung Kim; Hana Kim; Seungkwon Lee; Jiye Lee; Yeonil Jung
- Web page: https://patentgrep.com/patent/US20250098327A1

## CPC

- H10D 84/975: {Wiring regions or routing}
- H10D 89/10: Integrated device layouts
- H10D 84/907: {CMOS gate arrays}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

An integrated circuit includes devices arranged in a grid configuration and a first metal layer on the devices, wherein the grid includes first grid lines arranged in a first direction based on a first pitch and extending in a second direction, and second grid lines arranged in the second direction based on a second pitch and extending in the first direction. At least one of the plurality of devices includes gate lines extending in the second direction and having the first pitch, and the first metal layer includes first metal lines extending in the first direction and having the second pitch.

## Claims

### Claim 1

An integrated circuit comprising:
a plurality of devices arranged in a grid configuration; and
a first metal layer on the plurality of devices,
wherein the grid comprises:
a plurality of first grid lines arranged in a first direction based on a first pitch and extending in a second direction crossing the first direction; and
a plurality of second grid lines arranged in the second direction based on a second pitch and extending in the first direction,
wherein at least one of the plurality of devices comprises a plurality of gate lines extending in the second direction and having the first pitch, and
wherein the first metal layer comprises a plurality of first metal lines extending in the first direction and having the second pitch.

### Claim 2 (depends on 1)

The integrated circuit of claim 1,
wherein the plurality of devices comprise:
a first cell comprising first gate lines respectively overlapping the plurality of first grid lines, each of the first gate lines extending in the second direction; and
a second cell comprising at least one second gate line overlapping the plurality of first grid lines, the at least one second gate line extending in the second direction,
wherein the first pitch corresponds to a pitch of the first gate lines, and
wherein a first length of each of the first gate lines in the first direction is less than a second length of the at least one second gate line in the first direction.

### Claim 3 (depends on 2)

The integrated circuit of claim 2, wherein the second length is based on the first length and the first pitch.

### Claim 4 (depends on 3)

The integrated circuit of claim 3, wherein the second length is greater than or equal to a sum of the first length and the first pitch.

### Claim 5 (depends on 2)

The integrated circuit of claim 2,
wherein the first cell further comprises source/drain regions, each disposed between adjacent first grid lines among the plurality of first grid lines,
wherein a second metal layer comprising a plurality of second metal lines extend in the second direction, each of the plurality of second metal lines being electrically connected to the source/drain regions, and
wherein a pitch of the plurality of second metal lines is based on the first pitch.

### Claim 6 (depends on 2)

The integrated circuit of claim 2,
wherein the second cell further comprises source/drain regions disposed on opposing sides of the at least one second gate line,
wherein a second metal layer comprising a plurality of second metal lines extending in the second direction, each of the plurality of second metal lines being electrically connected to the source/drain regions, and
wherein a pitch of the plurality of second metal lines is based on the first pitch.

### Claim 7 (depends on 2)

The integrated circuit of claim 2, wherein the first cell comprises at least one of a standard cell, a static random-access memory device, or a logic device.

### Claim 8 (depends on 2)

The integrated circuit of claim 2, wherein the second cell comprises at least one of an input/output device, a one-time programmable device, an electro static discharge device, a passive device, or an analog device.

### Claim 9 (depends on 2)

The integrated circuit of claim 2, wherein at least one of the first cell or the second cell comprises active patterns, each active pattern extending in the first direction and respectively aligned with the plurality of second grid lines.

### Claim 10 (depends on 1)

The integrated circuit of claim 1, wherein the plurality of first metal lines are respectively aligned with the plurality of second grid lines.

### Claim 11

An integrated circuit comprising:
a plurality of cells arranged in a grid configuration having a first pitch,
wherein the grid comprises a plurality of grid lines arranged in a first direction based on the first pitch and extending in a second direction crossing the first direction,
wherein the plurality of cells comprise:
a first cell comprising first gate lines respectively overlapping first grid lines among the plurality of grid lines, each of the first gate lines extending in the second direction; and
a second cell comprising at least one second gate line overlapping second grid lines among the plurality of grid lines, the at least one second gate line extending in the second direction,
wherein the first pitch corresponds to a pitch of the first gate lines, and
wherein a first length of each of the first gate lines in the first direction is less than a second length of the at least one second gate line in the first direction.

### Claim 12 (depends on 11)

The integrated circuit of claim 11, wherein the second length is based on the first length and the first pitch.

### Claim 13 (depends on 11)

The integrated circuit of claim 11,
wherein the first cell further comprises source/drain regions, each disposed between adjacent first grid lines among the first grid lines,
wherein a metal layer comprising a plurality of metal lines extend in the second direction, each of the plurality of metal lines being electrically connected to the source/drain regions, and
wherein a pitch of the plurality of metal lines is based on the first pitch.

### Claim 14 (depends on 11)

The integrated circuit of claim 11,
wherein the second cell further comprises source/drain regions disposed on opposing sides of the at least one second gate line,
wherein a metal layer comprising a plurality of metal lines extending in the second direction, each of the plurality of metal lines being electrically connected to the source/drain regions, and
wherein a pitch of the plurality of metal lines is based on the first pitch.

### Claim 15 (depends on 11)

The integrated circuit of claim 11, wherein the first cell comprises at least one of a standard cell, a static random-access memory device, or a logic device.

### Claim 16 (depends on 11)

The integrated circuit of claim 11, wherein the second cell comprises at least one of an input/output device, a one-time programmable device, an electro static discharge device, a passive device, or an analog device.

### Claim 17

An integrated circuit comprising:
a plurality of blocks arranged in a grid configuration having a first pitch; and
a first metal layer on the plurality of blocks,
wherein the first metal layer comprises a plurality of first metal lines, each extending in a first direction and arranged apart from each other in a second direction crossing the first direction,
wherein the first pitch corresponds to a pitch of the plurality of first metal lines, and
wherein the grid comprises a plurality of grid lines extending in the first direction and arranged in the second direction based on the first pitch.

### Claim 18 (depends on 17)

The integrated circuit of claim 17,
wherein the plurality of grid lines correspond to horizontal grid lines,
wherein the grid further comprises a plurality of vertical grid lines extending in the second direction and arranged in the first direction based on a second pitch,
wherein the plurality of blocks comprise:
a first block comprising first gate lines respectively overlapping first grid lines among the plurality of vertical grid lines and each extending in the second direction; and
a second block comprising at least one second gate line overlapping second grid lines among the plurality of vertical grid lines and extending in the second direction,
wherein the second pitch corresponds to a pitch of the first gate lines, and
wherein a first length of each of the first gate lines in the first direction is less than a second length of the at least one second gate line in the first direction.

### Claim 19 (depends on 18)

The integrated circuit of claim 18, wherein the second length is based on the first length and the first pitch.

### Claim 20 (depends on 18)

The integrated circuit of claim 18,
wherein the first block comprises at least one of a standard cell, a static random-access memory device, or a logic device, and
wherein the second block comprises at least one of an input/output device, a one-time programmable device, an electro static discharge device, a passive device, or an analog device.