# US 2025/0098299 A1 · Array substrate and display panel > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0098299 A1 - Document ID: US20250098299A1 - Status: Published application - Kind: A1 - Application number: 18/292,969 - Filed: 2022-09-26 - Published: 2025-03-20 - Earliest claimed: 2022-09-26 - Assignees: Chongqing Boe Optoelectronics Technology Co., Ltd.; Boe Technology Group Co., Ltd. - Applicants: Chongqing BOE Optoelectronics Technology Co., Ltd.; BOE Technology Group Co., Ltd. - Inventors: Guodong YANG; Xiaoyuan WANG; Hui GUO; Chen XU; Bin WAN; Junming CHEN; Yan LIU; Xun PU; Yuanyuan ZHU - Web page: https://patentgrep.com/patent/US20250098299A1 ## CPC - H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies} - H10D 86/60: wherein the TFTs are in active matrices - G02F 1/133: Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements (arrangements or circuits for control of liquid crystal elements in a matrix, not structurally associated with these elements G09G3/36) - H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO} - H10D 86/441: {Interconnections, e.g. scanning lines} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS ## Abstract Provided is an array substrate. The array substrate includes a substrate, comprising a display region and a peripheral region surrounding the display region, the peripheral region at least including a gate-driver-on-array (GOA) region extending in a first direction; a plurality of thin film transistors, the plurality of thin film transistors being disposed at least in the GOA region; and a plurality of first patterns, wherein the plurality of first patterns are disposed at least on one side of the GOA region, the plurality of first patterns are spaced apart from the GOA region in the first direction, and a plurality of first patterns disposed on a same side of the GOA region are arranged in an array. ## Claims ### Claim 1 An array substrate, comprising: a substrate, comprising a display region and a peripheral region surrounding the display region, the peripheral region at least comprising a gate-driver-on-array (GOA) region extending in a first direction; a plurality of thin film transistors, the plurality of thin film transistors being disposed at least in the GOA region; and a plurality of first patterns, wherein the plurality of first patterns are disposed at least on one side of the GOA region, the plurality of first patterns are spaced apart from the GOA region in the first direction, and a plurality of first patterns disposed on a same side of the GOA region are arranged in an array; wherein the thin film transistor comprises a gate, a gate insulating layer, an active layer and a source/drain electrode layer which are sequentially laminated in a direction going away from the substrate, wherein the source/drain electrode layer comprises a source and a drain spaced apart from each other; and the plurality of first patterns are disposed in a same layer as at least one of the source and the drain. ### Claim 2 (depends on 1) The array substrate according to claim 1, wherein a shape of an orthographic projection of the first pattern on the substrate is a rectangle. ### Claim 3 (depends on 2) The array substrate according to claim 2, wherein the shape of the orthographic projection of the first pattern on the substrate is a square. ### Claim 4 (depends on 3) The array substrate according to claim 3, wherein one of two vertical boundaries of the first pattern is parallel to the first direction, and the other one of the two boundaries is parallel to a second direction; wherein the second direction is parallel to an arrangement direction of the display region and the GOA region, and the first direction intersects the second direction. ### Claim 5 (depends on 4) The array substrate according to claim 4, wherein a length of the first pattern along the first direction is m1, and a distance between any two adjacent first patterns along the first direction is n1, wherein m1/n1 ranges from 0.9 to 1.9; and a length of the first pattern along the second direction is m2, and a distance between any two adjacent first patterns along the second direction is n2, wherein m2/n2 ranges from 0.9 to 1.9. ### Claim 6 (depends on 1) The array substrate according to claim 1, wherein a minimum distance between orthographic projections of the plurality of first patterns on the substrate and orthographic projections of other structures in the array substrate on the substrate ranges from 15 μm to 30 μm. ### Claim 7 (depends on 1) The array substrate according to claim 1, wherein the peripheral region comprises two GOA regions extending along the first direction, and the two GOA regions are respectively located on two sides of the display region; wherein the plurality of first patterns are disposed on two sides of each of the two GOA regions. ### Claim 8 (depends on 1) The array substrate according to claim 1, wherein the peripheral region further comprises a fan-out region extending along a second direction, the second direction being parallel to an arrangement direction of the GOA region and the display region; and the array substrate further comprises: a plurality of second patterns, wherein the plurality of second patterns are disposed at least on one side of the fan-out region, the plurality of second patterns are spaced apart from the fan-out region along the second direction, a plurality of second patterns disposed on a same side of the fan-out region are arranged in an array, and the second pattern is different from the first pattern in at least one of the shape and size; wherein the plurality of second patterns comprise a plurality of first type of second patterns and a plurality of second type of second patterns, wherein the plurality of first type of second patterns are disposed in a same layer as the gate, and the plurality of second type of second patterns are disposed in a same layer as the source and the drain. ### Claim 9 (depends on 8) The array substrate according to claim 8, wherein orthographic projections of the plurality of first type of second patterns on the substrate are not overlapped with orthographic projections of the plurality of second type of second patterns on the substrate. ### Claim 10 (depends on 9) The array substrate according to claim 9, wherein the orthographic projections of the plurality of first type of second patterns on the substrate and the orthographic projections of the plurality of second type of second patterns on the substrate are alternately arranged along the second direction. ### Claim 11 (depends on 8) The array substrate according to claim 8, wherein a number of the plurality of first type of second patterns is equal to a number of the plurality of second type of second patterns, and the plurality of first type of second patterns are in one-to-one correspondence with the plurality of second type of second patterns; and an orthographic projection of each of the first type of second patterns on the substrate is overlapped with an orthographic projection of one corresponding second type of second pattern on the substrate. ### Claim 12 (depends on 8) The array substrate according to claim 8, wherein a shape of an orthographic projection of the second pattern on the substrate is rectangular, and a length of the second pattern along the first direction is greater than a length of the second pattern along the second direction. ### Claim 13 (depends on 12) The array substrate according to claim 12, wherein one of two vertical boundaries of the second pattern is parallel to the first direction, and the other one of the two vertical boundary is parallel to the second direction. ### Claim 14 (depends on 13) The array substrate according to claim 13, wherein the length of the second pattern along the first direction is r1, and a distance between any two adjacent second patterns along the first direction is s1, wherein r1/s1 ranges from 0.9 to 1.9; and the length of the second pattern along the second direction is r2, and a distance between any two adjacent second patterns along the second direction is s2, wherein r2/s2 ranges from 0.9 to 1.9. ### Claim 15 (depends on 8) The array substrate according to claim 8, wherein a minimum distance between orthographic projections of the second patterns on the substrate and orthographic projections of other structures in the array substrate on the substrate ranges from 75 μm to 100 μm. ### Claim 16 (depends on 8) The array substrate according to claim 8, wherein the plurality of second patterns are disposed on two sides of the fan-out region. ### Claim 17 (depends on 1) The array substrate according to claim 1, wherein the plurality of thin film transistors disposed in the GOA region constitute a plurality of cascaded shift register units, wherein each of the shift register units comprises eighteen thin film transistors and one storage capacitor. ### Claim 18 (depends on 1) The array substrate according to claim 1, wherein an active layer of the thin film transistor made of a metal oxide material. ### Claim 19 A display panel, comprising a plurality of light-emitting units and an array substrate; wherein the array substrate includes: a substrate, comprising a display region and a peripheral region surrounding the display region, the peripheral region at least comprising a gate-driver-on-array (GOA) region extending in a first direction; a plurality of thin film transistors, the plurality of thin film transistors being disposed at least in the GOA region; and a plurality of first patterns, wherein the plurality of first patterns are disposed at least on one side of the GOA region, the plurality of first patterns are spaced apart from the GOA region in the first direction, and a plurality of first patterns disposed on a same side of the GOA region are arranged in an array; wherein the thin film transistor comprises a gate, a gate insulating layer, an active layer and a source/drain electrode layer which are sequentially laminated in a direction going away from the substrate, wherein the source/drain electrode layer comprises a source and a drain spaced apart from each other; and the plurality of first patterns are disposed in a same layer as at least one of the source and the drain; the plurality of light-emitting units are disposed in the display region of the array substrate. ### Claim 20 (depends on 19) The display panel according to claim 19, wherein a shape of an orthographic projection of the first pattern on the substrate is a rectangle.