# US 2025/0098291 A1 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0098291 A1 - Document ID: US20250098291A1 - Status: Published application - Kind: A1 - Application number: 18/962,141 - Filed: 2024-11-27 - Published: 2025-03-20 - Earliest claimed: 2021-06-29 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Ho-Jun KIM; Hyungjin PARK - Web page: https://patentgrep.com/patent/US20250098291A1 ## CPC - H10D 84/834: {comprising FinFETs} - H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 84/0151: {Manufacturing their isolation regions} - H10D 84/0158: {the components including FinFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels} - B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic - H10D 62/121: {oriented parallel to substrates} - H10D 84/0135: {Manufacturing their gate conductors} - H10D 84/0153: {using gate cut processes} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES ## Abstract A semiconductor device including a substrate; gate structures spaced apart from each other on the substrate, each gate structure including a gate electrode and a gate capping pattern; source/drain patterns on opposite sides of the gate structures; first isolation patterns that respectively penetrate adjacent gate structures; and a second isolation pattern that extends between adjacent source/drain patterns, and penetrates at least one gate structure, wherein each first isolation pattern separates the gate structures such that the gate structures are spaced apart from each other, the first isolation patterns are aligned with each other, and top surfaces of the first and second isolation patterns are each located at a level the same as or higher than a level of a top surface of the gate capping pattern. ## Claims ### Claim 1 A method for forming a semiconductor device, comprising: forming a lower dielectric layer on a substrate; forming a plurality of gate structures in the lower dielectric layer, the plurality of gate structures spaced apart from each other in a first direction and extending in a second direction intersecting the first direction, the first and second directions being parallel to an upper surface of the substrate, each gate structure of the plurality of gate structures including a gate electrode and a gate capping pattern on the gate electrode; forming a cutting mask pattern on the lower dielectric layer and on the plurality of gate structures, the cutting mask pattern having holes that include first regions spaced apart from and align with each other along the first direction and a second region elongated along the second direction, the first regions exposing portions of the gate capping patterns of corresponding ones of the plurality of gate structures, respectively, and the second region exposing a portion of the gate capping pattern of a corresponding one of the plurality of gate structures; forming through holes penetrating corresponding ones of the plurality of gate structures by etching the plurality of gate structures using the cutting mask pattern as an etching mask, each of the through holes including first holes spaced apart from and aligned with each other along the first direction and a second hole elongated along the second direction, each of the first and second holes penetrating the gate capping pattern and the gate electrode of a corresponding one of the plurality of gate structures; and forming first isolation patterns in the first holes and a second isolation pattern in the second hole, wherein the first isolation patterns are spaced apart from and aligned with each other along the first direction, and the second isolation pattern is elongated along the second direction, and wherein top surfaces of the first isolation patterns and a top surface of the second isolation pattern are each located at a level the same as or higher than a level of a top surface of the gate capping pattern of each of the plurality of gate structures. ### Claim 2 (depends on 1) The method as claimed in claim 1, wherein forming the first and second isolation patterns comprises: forming an isolation layer that fills the through holes; and performing a planarization process on the isolation layer until reaching a top surface of the lower dielectric layer. ### Claim 3 (depends on 1) The method as claimed in claim 1, wherein a top surface of the lower dielectric layer is located at a level the same as or higher than the level of the top surface of the gate capping pattern of each gate structure of the plurality of gate structures. ### Claim 4 (depends on 1) The method as claimed in claim 1, wherein the second isolation pattern is connected to at least one first isolation pattern of the first isolation patterns to form a single unitary body. ### Claim 5 (depends on 1) The method as claimed in claim 1, wherein the top surfaces of the first isolation patterns and the top surface of the second isolation pattern are coplanar with each other. ### Claim 6 (depends on 1) The method as claimed in claim 1, wherein each of the first isolation patterns separates a corresponding gate structure of the plurality of gate structures into two gate structures that are spaced apart from each other in the second direction. ### Claim 7 (depends on 1) The method as claimed in claim 1, wherein heights of the first isolation patterns and a height of the second isolation pattern are substantially the same as each other. ### Claim 8 (depends on 1) The method as claimed in claim 1, wherein: each of the first isolation patterns has a first width in the first direction, and a first width of an odd-numbered first isolation pattern of the first isolation patterns is different from a first width of an even-numbered first isolation pattern of the first isolation patterns. ### Claim 9 (depends on 1) The method as claimed in claim 1, wherein: each of the first isolation patterns has a first width in the first direction, and the first widths of the first isolation patterns are substantially the same as each other. ### Claim 10 (depends on 1) The method as claimed in claim 1, further comprising: a plurality of active patterns that extend in the first direction on the substrate; and a device isolation layer between the plurality of active patterns, wherein bottom surfaces of the first isolation patterns and a bottom surface of the second isolation pattern are each located at a level lower than a level of a top surface of the device isolation layer. ### Claim 11 A method for forming a semiconductor device, comprising: forming a plurality of active patterns on a substrate and extending in a first direction; forming a plurality of gate structures that are spaced apart from each other in the first direction on the substrate, the plurality of gate structures extending in a second direction intersecting the first direction, and crossing the plurality of active patterns; forming a plurality of source/drain patterns on the plurality of active patterns on opposite sides of each gate structure of the plurality of gate structures; forming a plurality of first isolation patterns that correspondingly penetrate adjacent gate structures of the plurality of gate structures, the plurality of first isolation patterns being aligned in the first direction; and forming a second isolation pattern that extends in the second direction between adjacent source/drain patterns of the plurality of source/drain patterns, and that penetrates at least one gate structure of the plurality of gate structures, wherein each first isolation pattern of the plurality of first isolation patterns separates two gate structures of the plurality of gate structures such that the two gate structures of the plurality of gate structures are spaced apart from each other in the second direction, and wherein a bottom surface of the second isolation pattern is substantially coplanar with a bottom surface of one first isolation pattern of the plurality of first isolation patterns. ### Claim 12 (depends on 11) The method as claimed in claim 11, wherein the second isolation pattern is connected to at least one first isolation pattern of the first isolation patterns to form a single unitary body. ### Claim 13 (depends on 11) The method as claimed in claim 11, wherein: each gate structure of the plurality of gate structures includes a gate electrode and a gate capping pattern on the gate electrode, and top surfaces of the plurality of first isolation patterns and a top surface of the second isolation pattern are each located at a level the same as or higher than a level of a top surface of the gate capping pattern of each gate structure of the plurality of gate structures. ### Claim 14 (depends on 11) The method as claimed in claim 11, further comprising: forming a plurality of first contacts on opposite sides of each gate structure of the plurality of gate structures and correspondingly connected to the plurality of source/drain patterns, wherein top surfaces of the plurality of first contacts are located at a level higher than the level of the top surface of the gate capping pattern of each gate structure of the plurality of gate structures. ### Claim 15 (depends on 11) The method as claimed in claim 11, further comprising: forming a lower dielectric layer between the plurality of gate structures and extending between adjacent first isolation patterns of the plurality of first isolation patterns, wherein a top surface of the lower dielectric layer, top surfaces of the plurality of first isolation patterns, and a top surface of the second isolation pattern are located at substantially the same level. ### Claim 16 (depends on 11) The method as claimed in claim 11, wherein forming the first and second isolation patterns comprises: forming first holes that correspondingly penetrate adjacent gate structures of the plurality of gate structures, the first holes spaced apart from and aligned with each other along the first direction; forming a second hole that extends in the second direction between adjacent source/drain patterns of the plurality of source/drain patterns, and that penetrates at least one gate structure of the plurality of gate structures; forming an isolation layer that fills the first holes and the second hole; and performing a planarization process on the isolation layer. ### Claim 17 (depends on 11) The method as claimed in claim 11, further comprising: a device isolation layer between the plurality of active patterns, wherein bottom surfaces of the first isolation patterns and the bottom surface of the second isolation pattern are each located at a level lower than a level of a top surface of the device isolation layer. ### Claim 18 (depends on 11) The method as claimed in claim 11, wherein the plurality of first isolation patterns and the second isolation pattern include the same material as each other. ### Claim 19 A method for forming a semiconductor device, comprising: forming a lower dielectric layer on a substrate; forming a plurality of gate structures in the lower dielectric layer, the plurality of gate structures spaced apart from each other in a first direction and extending in a second direction intersecting the first direction, the first and second directions being parallel to an upper surface of the substrate; forming a cutting mask pattern on the lower dielectric layer and on the plurality of gate structures, the cutting mask pattern having holes that include first regions spaced apart from and align with each other along the first direction and a second region elongated along the second direction, the first regions exposing portions of corresponding gate structures of the plurality of gate structures, respectively, and the second region exposing a portion of a corresponding gate structure of the plurality of gate structures; forming through holes penetrating corresponding gate structures of the plurality of gate structures by etching the plurality of gate structures using the cutting mask pattern as an etching mask, each of the through holes including first holes spaced apart from and aligned with each other along the first direction and a second hole elongated along the second direction, each of the first and second holes penetrating a corresponding gate structure of the plurality of gate structures; and forming first isolation patterns in the first holes and a second isolation pattern in the second hole, wherein the first isolation patterns are spaced apart from and aligned with each other along the first direction, and the second isolation pattern is elongated along the second direction, and wherein the first isolation patterns and the second isolation pattern include the same material as each other. ### Claim 20 (depends on 19) The method as claimed in claim 19, wherein each gate structure of the plurality of gate structures includes a gate electrode and a gate capping pattern on the gate electrode, and wherein top surfaces of the first isolation patterns and a top surface of the second isolation pattern and a top surface of the lower dielectric layer are each located at a level the same as or higher than a level of a top surface of the gate capping pattern of each of the plurality of gate structures.