# US 2025/0098290 A1 · High-voltage device and method of forming the same

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- Number: US 2025/0098290 A1
- Document ID: US20250098290A1
- Status: Published application
- Kind: A1
- Application number: 18/883,030
- Filed: 2024-09-12
- Published: 2025-03-20
- Earliest claimed: 2023-09-14
- Assignees: Nuvoton Technology Corporation
- Applicants: Nuvoton Technology Corporation
- Inventors: Vivek NINGARAJU; Chin-Han PAN; Hong-Xiu CHEN
- Web page: https://patentgrep.com/patent/US20250098290A1

## CPC

- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 8/043: {of planar diodes}
- H10D 8/411: {PN diodes having planar bodies}
- H10D 30/0512: {of FETs having PN homojunction gates}
- H10D 30/83: FETs having PN junction gate electrodes
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 62/343: {Gate regions of field-effect devices having PN junction gates}
- H10D 64/111: {Field plates}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 32/1406: {by ion implantation}
- H10P 32/171: {being group IV material}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A high-voltage device includes: a diode; a junction field-effect transistor (JFET) adjoining the diode and electrically coupled to the diode; a high-voltage junction termination (HVJT) element electrically connected with the diode and the junction field-effect transistor, wherein the high-voltage junction termination element is a ring shape from top view, and a high-side region and a low-side region are respectively defined inside the ring shape and outside the ring shape; and a first deep well region encircling the high-side region. The first deep well region includes: a first segment disposed in the high-voltage junction termination element; and a second segment disposed in the junction field-effect transistor. The first segment includes a well region and a doped region in the well region. The second segment includes only the well region.

## Claims

### Claim 1

A high-voltage device, comprising:
a diode;
a junction field-effect transistor (JFET) adjoining the diode and electrically coupled to the diode;
a high-voltage junction termination (HVJT) element electrically connected with the diode and the junction field-effect transistor, wherein the high-voltage junction termination element is a ring shape from top view, and a high-side region and a low-side region are respectively defined inside the ring shape and outside the ring shape; and
a first deep well region encircling the high-side region, comprising:
a first segment disposed in the high-voltage junction termination element, wherein the first segment comprises a well region and a doped region in the well region; and
a second segment disposed in the junction field-effect transistor, wherein the second segment comprises only the well region.

### Claim 2 (depends on 1)

The high-voltage device of claim 1, further comprising:
a substrate disposed across the high-voltage junction termination element, the diode, and the junction field-effect transistor, and having a first conductive type; and
an epitaxial layer disposed across the high-voltage junction termination element, the diode, and the junction field-effect transistor, and is on the substrate, wherein the epitaxial layer has a second conductive type different from the first conductive type.

### Claim 3 (depends on 2)

The high-voltage device of claim 2, wherein the first deep well region is disposed in the epitaxial layer, and has the second conductive type.

### Claim 4 (depends on 2)

The high-voltage device of claim 2, wherein the diode further comprising:
a first high-voltage well region disposed in the epitaxial layer, and having the first conductive type;
a second deep well region disposed in the epitaxial layer and laterally encircling the first high-voltage well region, and having the second conductive type; and
a second high-voltage well region disposed in the epitaxial layer and laterally encircling the second deep well region, and having the first conductive type.

### Claim 5 (depends on 4)

The high-voltage device of claim 4, wherein the diode further comprising a first buried layer disposed in the substrate, and the first buried layer is in direct contact with the first high-voltage well region and the second deep well region.

### Claim 6 (depends on 4)

The high-voltage device of claim 4, wherein the first high-voltage well region comprises a first doped region and a second doped region, the second deep well region comprises a third doped region, and the second high-voltage well region comprises a fourth doped region.

### Claim 7 (depends on 6)

The high-voltage device of claim 6, wherein the second doped region encircles the first doped region, the third doped region encircles the second doped region, and the fourth doped region encircles the third doped region.

### Claim 8 (depends on 7)

The high-voltage device of claim 7, wherein the junction field-effect transistor further comprising:
a fifth doped region disposed in the epitaxial layer, and having the second conductive type;
a sixth doped region disposed in the epitaxial layer, and having the first conductive type; and
a second buried layer disposed in the substrate, and located under the sixth doped region.

### Claim 9 (depends on 8)

The high-voltage device of claim 8, further comprising:
an interlayer dielectric (ILD) layer disposed on the epitaxial layer;
a first metal layer and a second metal layer disposed on the interlayer dielectric layer;
an inter-metal dielectric (IMD) layer covering the interlayer dielectric layer, the first metal layer, and the second metal layer; and
a third metal layer and a fourth metal layer disposed on the inter-metal dielectric layer.

### Claim 10 (depends on 9)

The high-voltage device of claim 9, wherein the first metal layer is electrically coupled to the second doped region and the third doped region respectively through a first via and a second via.

### Claim 11 (depends on 9)

The high-voltage device of claim 9, wherein the second metal layer is electrically coupled to the fourth doped region through a third via.

### Claim 12 (depends on 9)

The high-voltage device of claim 9, wherein the third metal layer is electrically coupled to the first doped region and the fifth doped region respectively through a fourth via and a fifth via.

### Claim 13 (depends on 9)

The high-voltage device of claim 9, wherein the fourth metal layer is electrically coupled to the sixth doped region through a sixth via.

### Claim 14

A method of forming a high-voltage device, comprising:
providing a substrate;
forming an epitaxial layer on the substrate;
forming a first high-voltage well region, a first deep well region encircling the first high-voltage well region, and a second high-voltage well region encircling the first deep well region in a first region of the epitaxial layer;
forming a first doped region and a second doped region encircling the first doped region in the first high-voltage well region;
forming a third doped region in the first deep well region, wherein the third doped region encircles the second doped region;
forming a fourth doped region in the second high-voltage well region;
forming a fifth doped region and a sixth doped region in a second region of the epitaxial layer, wherein the second region laterally adjoins the first region;
extending a side of the fourth doped region outward into a third region of the epitaxial layer to form a loop, wherein the second region is in the loop;
forming a second deep well region in the loop, wherein the second deep well region extends along an inner side of the loop and across the second region;
forming a seventh doped region in the second deep well region, wherein the seventh doped region extends along a profile of the second deep well region; and
cutting off a portion of the seventh doped region in the second deep well region across the second region.

### Claim 15 (depends on 14)

The method of claim 14, wherein the first region, the second region, and the third region respectively define a diode, a junction field-effect transistor, and a high-voltage junction termination element.

### Claim 16 (depends on 14)

The method of claim 14, further comprising forming a first buried layer and a second buried layer in the substrate, the first buried layer and the second buried layer respectively extend into the first region and the second region of the epitaxial layer.

### Claim 17 (depends on 14)

The method of claim 14, further comprising forming an eighth doped region and a conductive structure between the loop of the third region and the second deep well region.

### Claim 18 (depends on 17)

The method of claim 17, wherein a first distance is between the conductive structure and the seventh doped region.

### Claim 19 (depends on 18)

The method of claim 18, wherein before cutting off the portion of the seventh doped region across the second region, a second distance is between a portion of the sixth doped region and a portion of the seventh doped region across the second region, and the second distance is different from the first distance.

### Claim 20 (depends on 17)

The method of claim 17, wherein the first doped region of the first region is electrically coupled to the fifth doped region of the second region through a metal layer.