# US 2025/0098285 A1 · Silicon carbide semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0098285 A1 - Document ID: US20250098285A1 - Status: Published application - Kind: A1 - Application number: 18/970,414 - Filed: 2024-12-05 - Published: 2025-03-20 - Earliest claimed: 2020-03-17 - Assignees: Fuji Electric Co., Ltd. - Applicants: Fuji Electric Co., Ltd. - Inventors: Hiroyuki FUJISAWA; Akimasa KINOSHITA - Web page: https://patentgrep.com/patent/US20250098285A1 ## CPC - H10D 84/148: {the built-in components being breakdown diodes, e.g. Zener diodes} - H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes} - H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors} - H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)} - H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs} - H10D 62/307: {the doping variations being parallel to the channel lengths} - H10D 84/144: {in antiparallel diode configurations} - H10D 62/157: {Impurity concentrations or distributions} - H10D 62/8325: {Silicon carbide} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, gate insulating films, gate electrodes, an insulating film, first electrodes, a second electrode, and trenches. The first semiconductor regions and the second semiconductor regions are periodically disposed apart from one another in a first direction in which the trenches extend in a stripe pattern. ## Claims ### Claim 1 A semiconductor device, comprising: a semiconductor base that includes a semiconductor substrate of a first conductivity type; a plurality of trenches provided at a first main surface of the semiconductor base, the plurality of trenches including a plurality of longitudinal portions that respectively extend in a first direction; a plurality of first semiconductor regions of the first conductivity type selectively provided at the first main surface of the semiconductor base so that each of the plurality of first semiconductor regions is in contact with a sidewall of at least a corresponding one of the plurality of longitudinal portions; a bottom region of a second conductivity type provided so as to be in contact with a bottom of at least the corresponding one of the plurality of longitudinal portions; a semiconductor layer of the second conductivity type selectively provided at the first main surface of the semiconductor base so as to be in contact with the sidewall of at least the corresponding one of the plurality of longitudinal portions; and a plurality of connecting regions of the second conductivity type that are periodically provided in the semiconductor base aligned in the first direction, and that each connect the semiconductor layer to the bottom region, wherein the semiconductor layer includes a plurality of upper portions periodically provided in the semiconductor base aligned in the first direction to be exposed from the first main surface of the semiconductor base, and the plurality of connecting regions each extend in the first direction to an outside of one end and another end of a corresponding one of the plurality of upper portions. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the plurality of upper portions has an impurity concentration higher than an impurity concentration of the bottom region. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein in a plan view of the semiconductor device, an interval between an adjacent two of the plurality of upper portions that are adjacent to each other in the first direction is greater than a length in the first direction of each of the plurality of upper portions. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein in a plan view of the semiconductor device, an interval between an adjacent two of the plurality of upper portions that are adjacent to each other in the first direction is at least 2.514 μm. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, further comprising a mesa region between an adjacent two of the plurality of longitudinal portions that are adjacent to each other in a second direction orthogonal to the first direction, wherein at least one of the plurality of upper portions is provided across the mesa region. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein at least one of the upper portions is in contact with only one of an adjacent two of the plurality of longitudinal portions that are adjacent to each other in a second direction orthogonal to the first direction. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, further comprising a mesa region between an adjacent two of the plurality of longitudinal portions that are adjacent to each other in a second direction orthogonal to the first direction, wherein at least one of the plurality of first semiconductor regions is provided across the mesa region. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, further comprising: an interlayer insulating film provided on the first main surface of the semiconductor base; a contact hole that penetrates the interlayer insulating film in a depth direction; and a source electrode that is in contact with the plurality of first semiconductor regions and the plurality of upper portions on the first main surface via the contact hole. ### Claim 9 (depends on 1) The semiconductor device according to claim 1, wherein the semiconductor device is a trench-type SiC-MOSFET. ### Claim 10 A semiconductor device, comprising: a semiconductor base that includes a semiconductor substrate of a first conductivity type; a plurality of trenches provided at a first main surface of the semiconductor base, the plurality of trenches including a plurality of longitudinal portions that each extend in a first direction; a plurality of mesa regions each provided between a corresponding adjacent two of the plurality of longitudinal portions that are adjacent to each other in a second direction orthogonal to the first direction; and a bottom region of a second conductivity type provided so as to be in contact with a bottom of at least one of the plurality of longitudinal portions, wherein each mesa region includes: a semiconductor layer of the second conductivity type; a plurality of first semiconductor regions of the first conductivity type selectively provided at the first main surface of the semiconductor base so that each of the plurality of first semiconductor region is in contact with a sidewall of at least the one of the plurality of longitudinal portions; and a plurality of connecting regions of the second conductivity type periodically provided in the semiconductor base aligned in the first direction, the plurality of connecting regions each connecting the semiconductor layer to the bottom region, the semiconductor layer includes a plurality of upper portions, periodically provided in the semiconductor base aligned in the first direction to be exposed from the first main surface of the semiconductor base, and the plurality of connecting regions each extend in the first direction to an outside of one end and another end of a corresponding one of the plurality of upper portions. ### Claim 11 (depends on 10) The semiconductor device according to claim 10, wherein each of the plurality of connecting regions is provided from one to another of a corresponding adjacent two of the plurality of longitudinal portions that are adjacent to each other in the second direction. ### Claim 12 (depends on 10) The semiconductor device according to claim 10, wherein the bottom region has an impurity concentration higher than an impurity concentration of the semiconductor layer. ### Claim 13 (depends on 10) The semiconductor device according to claim 10, wherein the plurality of connecting regions has an impurity concentration higher than an impurity concentration of the semiconductor layer. ### Claim 14 (depends on 10) The semiconductor device according to claim 10, further comprising a gate electrode embedded in the at least one of the plurality of longitudinal portions via a gate insulating film. ### Claim 15 (depends on 14) The semiconductor device according to claim 14, wherein the plurality of mesa regions include: a first mesa region that includes the plurality of first semiconductor regions and the semiconductor layer that are in contact with the gate insulating film; and a second mesa region in which one of the plurality of connecting regions is provided between the corresponding adjacent two of the plurality of longitudinal portions. ### Claim 16 A semiconductor device, comprising: a semiconductor base that includes a semiconductor substrate of a first conductivity type; a plurality of trenches provided at a first main surface of the semiconductor base, the plurality of trenches including a plurality of longitudinal portions that each extend in a first direction; a plurality of mesa regions each provided between a corresponding adjacent two of the plurality of longitudinal portions that are adjacent in a second direction orthogonal to the first direction; and a plurality of bottom regions of a second conductivity type provided so as to be in contact with bottoms of the plurality of longitudinal portions, respectively, wherein each mesa region includes: a semiconductor layer of the second conductivity type; a first semiconductor region of the first conductivity type selectively provided at the first main surface of the semiconductor base so as to be in contact with a sidewall of one of the corresponding adjacent two of the plurality of longitudinal portions; and a plurality of connecting regions of the second conductivity type periodically provided in the semiconductor base in the first direction, the plurality of connecting regions connecting the semiconductor layer to corresponding two of the plurality of bottom regions that are respectively in contact with the corresponding adjacent two of the plurality of longitudinal portions that form said mesa region, the semiconductor layer includes a plurality of upper portions periodically provided in the semiconductor base in the first direction to be exposed from the first main surface of the semiconductor base, and the plurality of connecting regions each extend in the first direction to an outside of one end and another end of a corresponding one of the plurality of upper portions. ### Claim 17 (depends on 16) The semiconductor device according to claim 16, wherein the plurality of upper portions has an impurity concentration higher than an impurity concentration of the plurality of bottom regions.