# US 2025/0098283 A1 · Semiconductor structure

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- Number: US 2025/0098283 A1
- Document ID: US20250098283A1
- Status: Published application
- Kind: A1
- Application number: 18/971,358
- Filed: 2024-12-06
- Published: 2025-03-20
- Earliest claimed: 2017-09-12
- Assignees: Mediatek Inc.
- Applicants: Mediatek Inc.
- Inventors: Po-Chao TSAO
- Web page: https://patentgrep.com/patent/US20250098283A1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0156: {Manufacturing their doped wells}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/853: {comprising FinFETs}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 20/021: {of interconnections within wafers or substrates}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0698: {Local interconnections}
- H10W 20/427: {Power or ground buses}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure includes a substrate, a first well region on the substrate, a shallow trench isolation (STI) region over the first well region, and a first transistor. The first transistor includes a first fin formed on the first well region, a first gate electrode formed on the first fin, and a first doping region formed on the first fin. The semiconductor structure further includes a first power rail on the first well region and in the STI region and a first source/drain contact over the first doping region and the first power rail to electrically connect the first doping region to the first power rail. A bottom surface of first source/drain contact is in direct contact with the STI region.

## Claims

### Claim 1

A semiconductor structure, comprising:
a substrate;
a first well region on the substrate;
a shallow trench isolation (STI) region over the first well region;
a first transistor, comprising:
a first fin formed on the first well region;
a first gate electrode formed on the first fin; and
a doping region formed on the first fin;
a first power rail on the first well region and in the STI region; and
a first source/drain contact over the first doping region and the first power rail to electrically connect the first doping region to the first power rail, wherein a bottom surface of first source/drain contact is in direct contact with the STI region.

### Claim 2 (depends on 1)

The semiconductor structure as claimed in claim 1, further comprising:
a barrier layer separating the first power rail from the first well region and the STI region.

### Claim 3 (depends on 1)

The semiconductor structure as claimed in claim 1, wherein the first doping region is an N-type doping region, and the first power rail is electrically coupled to VSS.

### Claim 4 (depends on 3)

The semiconductor structure as claimed in claim 3, wherein the first transistor is a NMOS transistor, and the first well region is doped with p-type dopants.

### Claim 5 (depends on 1)

The semiconductor structure as claimed in claim 1, wherein the first doping region is a P-type doping region, and the first power rail is electrically coupled to VDD.

### Claim 6 (depends on 5)

The semiconductor structure as claimed in claim 5, wherein the first transistor is a PMOS transistor, and the first well region is doped with n-type dopants.

### Claim 7 (depends on 1)

The semiconductor structure as claimed in claim 1, further comprising:
a second well region on the substrate, wherein the STI is over the second well region;
a second transistor, comprising:
a second fin formed on the second well region;
a second gate electrode formed on the second fin; and
a second doping region formed on the second fin;
a second power rail on the second well region and in the STI region;
a second source/drain contact over the second doping region and the second power rail to electrically connect the second doping region to the second power rail, wherein the a bottom surface of second source/drain contact is in direct contact with the STI region; and
an interlayer dielectric (ILD) layer over the STI region and between the first source/drain contact and the second source/drain contact.

### Claim 8 (depends on 7)

The semiconductor structure as claimed in claim 7,
wherein the first well region is an N-type well region and the second well region is a P-type well region,
wherein the first doping region is a P-type doping region and the second doping region is an N-type well region.

### Claim 9 (depends on 8)

The semiconductor structure as claimed in claim 8, wherein the first power rail is electrically coupled to VDD and the first power rail is electrically coupled to VSS.

### Claim 10 (depends on 1)

The semiconductor structure as claimed in claim 1, further comprising:
a blocking layer on sidewalls of the first source/drain contact.

### Claim 11

A semiconductor structure, comprising:
a first well region and a second well region on the substrate, wherein the first well region and the second well region have different types of dopants;
a shallow trench isolation (STI) region on the first well region and the second well region;
a cell, comprising:
a first transistor over the first well region; and
a second transistor over the second well region;
an interlayer dielectric (ILD) layer over the STI region and between the first transistor and the second transistor;
a VDD line formed in the STI region over the first well region;
a VSS line formed in the STI region over the second well region;
a first source/drain contact over and electrically connected to the VDD line and a source region of the first transistor; and
a second source/drain contact over and electrically connected to the VSS line and a source region of the second transistor,
wherein the first source/drain contact and the second source/drain contact are in direct contact with a top surface of the STI region.

### Claim 12 (depends on 11)

The semiconductor structure as claimed in claim 11, wherein the cell comprises a standard cell or a memory cell.

### Claim 13 (depends on 11)

The semiconductor structure as claimed in claim 11, further comprising:
barrier layers over the first well region and the second well region and under and in contact with the VDD line and the VSS line.

### Claim 14 (depends on 11)

The semiconductor structure as claimed in claim 11, further comprising:
blocking layers on sidewalls of the STI region.

### Claim 15 (depends on 11)

The semiconductor structure as claimed in claim 11, wherein the first transistor is a PMOS transistor and comprises:
first fins on the first well region;
P-type doping regions on the first fins,
wherein the first source/drain contact is over the P-type doping regions and electrically connects the P-type doping regions to the VDD line.

### Claim 16 (depends on 15)

The semiconductor structure as claimed in claim 15, wherein the second transistor is a NMOS transistor and comprises:
second fins on the second well region;
N-type doping regions on the second fins,
wherein the second source/drain contact is over the N-type doping regions and electrically connects the N-type doping regions to the VSS line.

### Claim 17

A semiconductor structure, comprising:
a substrate;
an N-type well region and a P-type well region on the substrate;
a shallow trench isolation (STI) region on the N-type well region and the P-type well region;
a PMOS transistor, comprising:
first fins formed on the N-type well region; and
P-type doping regions formed on the first fins;
a NMOS transistor, comprising:
second fins formed on the P-type well region; and
N-type doping regions formed on the second fins;
a first power rail over the N-type well region and electrically coupled to VDD;
a second power rail over the P-type well region and electrically coupled to VSS;
a first source/drain contact over and electrically connected to the first power rail and the P-type doping regions;
a second source/drain contact over and electrically connected to the second power rail and the N-type doping regions; and
an interlayer dielectric (ILD) layer over the STI region and between the first transistor and the second transistor,
wherein the first source/drain contact and the second source/drain contact are vertically in contact with the STI region.

### Claim 18 (depends on 17)

The semiconductor structure as claimed in claim 17, further comprising:
barrier layers on sidewalls and bottom surfaces of the first power rail and the second power rail.

### Claim 19 (depends on 18)

The semiconductor structure as claimed in claim 18, further comprising:
blocking layers on sidewalls of the first source/drain contact and the second source/drain contact, wherein the blocking layers are over and in contact with the barrier layers.

### Claim 20 (depends on 19)

The semiconductor structure as claimed in claim 19, wherein sidewalls of the STI region are in contact with barrier layers and the blocking layers.