# US 2025/0098280 A1 · Semiconductor method and device

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- Number: US 2025/0098280 A1
- Document ID: US20250098280A1
- Status: Published application
- Kind: A1
- Application number: 18/965,045
- Filed: 2024-12-02
- Published: 2025-03-20
- Earliest claimed: 2021-07-09
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yi-Cheng Li; Pin-Ju Liang; Ta-Chun Ma; Pei-Ren Jeng; Yee-Chia Yeo
- Web page: https://patentgrep.com/patent/US20250098280A1

## CPC

- H10D 84/0167: {Manufacturing their channels}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/751: {having composition variations in the channel regions}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/853: {comprising FinFETs}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 50/642: {Chemical etching}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes forming a fin extending from a substrate; depositing a liner over a top surface and sidewalls of the fin, where the minimum thickness of the liner is dependent on selected according to a first germanium concentration of the fin; forming a shallow trench isolation (STI) region adjacent the fin; removing a first portion of the liner on sidewalls of the fin, the first portion of the liner being above a topmost surface of the STI region; and forming a gate stack on sidewalls and a top surface of the fin, where the gate stack is in physical contact with the liner.

## Claims

### Claim 1

A method comprising:
forming a fin extending from an n-well region of a substrate, the fin comprising a first portion that includes a first material, and a second portion below the first portion comprising a second material that is different from the first material;
forming a semiconductor liner over a top surface and sidewalls of the fin, wherein the semiconductor liner comprises a third material that is different from the first material;
forming a shallow trench isolation (STI) region adjacent the fin;
removing a first portion of the semiconductor liner on the sidewalls of the fin, the first portion of the semiconductor liner being above a topmost surface of the STI region, wherein after removing the first portion of the semiconductor liner, a top surface of the semiconductor liner is above the topmost surface of the STI region; and
forming a gate stack on sidewalls and a top surface of the fin, wherein the gate stack is in physical contact with the semiconductor liner.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first portion of the fin comprises silicon germanium.

### Claim 3 (depends on 1)

The method of claim 1, wherein the second portion of the fin comprises silicon.

### Claim 4 (depends on 1)

The method of claim 1, wherein the semiconductor liner comprises silicon, and wherein the semiconductor liner has a first thickness that is in a range from 0.5 nm to 5 nm.

### Claim 5 (depends on 1)

The method of claim 1, wherein removing the first portion of the semiconductor liner on the sidewalls of the fin comprises performing a wet etching process using hydrofluoric acid as an etchant.

### Claim 6 (depends on 1)

The method of claim 1, wherein a first width of the first portion of the fin is smaller than a second width of the second portion of the fin.

### Claim 7 (depends on 1)

The method of claim 1, wherein forming the semiconductor liner comprises performing a deposition process that takes place at a process temperature in a range from 350° C. to 500° C. and a process pressure in a range from 0.5 mtorr to 3 mtorr.

### Claim 8

A method comprising:
forming a first epitaxial layer over a substrate, wherein a first material of the first epitaxial layer is different from a second material of the substrate;
patterning the first epitaxial layer and the substrate to form a fin that protrudes from the substrate, wherein the fin comprises a first portion that comprises the first material and a second portion below the first portion that comprises the second material, wherein the first material comprises silicon germanium having a first germanium concentration that is in a range from 20 atomic percent to 80 atomic percent;
depositing a semiconductor liner over a top surface and sidewalls of the fin,
forming a shallow trench isolation (STI) region adjacent the fin, wherein the fin protrudes above a top surface of the STI region; and
etching a first portion of the semiconductor liner on the sidewalls of the fin.

### Claim 9 (depends on 8)

The method of claim 8, wherein the second material is silicon.

### Claim 10 (depends on 8)

The method of claim 8, wherein a first height of the STI region that is closer to a sidewall of the semiconductor liner is larger than a second height of the STI region that is further away from the sidewall of the semiconductor liner.

### Claim 11 (depends on 8)

The method of claim 8, wherein etching the first portion of the semiconductor liner on the sidewalls of the fin comprises performing a wet etching process using ozone (O3) as an etchant.

### Claim 12 (depends on 8)

The method of claim 8, wherein etching the first portion of the semiconductor liner on the sidewalls of the fin comprises performing a wet etching process using hydrofluoric acid as an etchant.

### Claim 13 (depends on 8)

The method of claim 8, wherein the semiconductor liner comprises silicon, and wherein the semiconductor liner comprises a first thickness that is in a range from 0.5 nm to 5 nm.

### Claim 14 (depends on 8)

The method of claim 8, further comprising forming a gate stack on sidewalls and a top surface of the fin, wherein the gate stack is in physical contact with the semiconductor liner.

### Claim 15

A device comprising:
a semiconductor fin protruding from a substrate, the semiconductor fin comprising:
a first portion comprising a first material; and
a second portion below the first portion, wherein the second portion comprises a second material different from the first material;
a semiconductor liner on sidewalls of the second portion of the semiconductor fin; and
a shallow trench isolation (STI) region adjacent the semiconductor fin, wherein a top surface of the semiconductor liner is above a topmost surface of the STI region; and
a gate stack on sidewalls and a top surface of the first portion of the semiconductor fin, wherein the gate stack is in physical contact with the semiconductor liner.

### Claim 16 (depends on 15)

The device of claim 15, wherein the first material comprises silicon germanium, and the second material comprises silicon.

### Claim 17 (depends on 16)

The device of claim 16, wherein a germanium concentration of the first portion of the semiconductor fin is in a range from 20 atomic percent to 80 atomic percent.

### Claim 18 (depends on 15)

The device of claim 15, wherein the first portion of the semiconductor fin has a first width that is smaller than a second width of the second portion of the semiconductor fin.

### Claim 19 (depends on 15)

The device of claim 15, where the semiconductor liner comprises silicon.

### Claim 20 (depends on 19)

The device of claim 19, wherein the semiconductor liner comprises a first thickness that in a range from 0.5 nm to 5 nm.