# US 2025/0098276 A1 · Semiconductor device structure and methods of forming the same

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- Number: US 2025/0098276 A1
- Document ID: US20250098276A1
- Status: Published application
- Kind: A1
- Application number: 18/369,099
- Filed: 2023-09-15
- Published: 2025-03-20
- Earliest claimed: 2023-09-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Kai-Chun CHANG; Chi-Hsun LIN; Yi Chen HO; Hung Cheng LIN
- Web page: https://patentgrep.com/patent/US20250098276A1

## CPC

- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/852: {comprising forksheet IGFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Methods for forming a semiconductor device structure are described. The method includes forming first and second fin structures over a substrate and forming a dielectric wall between the first and second fin structures. The forming the dielectric wall includes depositing a first dielectric layer between the first and second fin structures, and a seam is formed in the first dielectric layer. The forming the dielectric wall further includes performing an anisotropic etch process to remove a portion of the first dielectric layer to expose the seam, performing an isotropic etch process to enlarge an opening of the seam, and the seam has a “V” shaped cross-sectional profile. The forming the dielectric wall further includes depositing a second dielectric layer between the first and second fin structures, and the seam is filled. The method further includes forming shallow trench isolation regions adjacent the first and second fin structures.

## Claims

### Claim 1

A method, comprising:
forming first and second fin structures over a substrate;
forming a dielectric wall between the first and second fin structures, comprising:
depositing a first dielectric layer between the first and second fin structures, wherein a seam is formed in the first dielectric layer;
performing an anisotropic etch process to remove a portion of the first dielectric layer to expose the seam;
performing an isotropic etch process to enlarge an opening of the seam, wherein the seam has a “V” shaped cross-sectional profile; and
depositing a second dielectric layer between the first and second fin structures, wherein the seam is filled; and
forming shallow trench isolation regions adjacent the first and second fin structures.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first dielectric layer and the second dielectric layer comprise a same material.

### Claim 3 (depends on 2)

The method of claim 2, wherein the first dielectric layer and the second dielectric layer comprise SiCN, the first dielectric layer has a thickness ranging from about 7 nm to about 9 nm, and the second dielectric layer has a thickness ranging from about 3 nm to about 4 nm.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first dielectric layer is formed by atomic layer deposition.

### Claim 5 (depends on 4)

The method of claim 4, wherein the first dielectric layer and the second dielectric layer are formed by a same process.

### Claim 6 (depends on 4)

The method of claim 4, wherein the first dielectric layer and the second dielectric layer are formed by different processes.

### Claim 7 (depends on 1)

The method of claim 1, further comprising forming a third fin structure over the substrate prior to forming the dielectric wall.

### Claim 8 (depends on 7)

The method of claim 7, wherein the first dielectric layer and the second dielectric layer are formed between the second and third fin structures.

### Claim 9 (depends on 8)

The method of claim 8, further comprising removing the first and second dielectric layers formed between the second and third fin structures prior to forming shallow trench isolation regions.

### Claim 10

A method, comprising:
forming first, second, and third fin structures over a substrate;
depositing a liner layer around the first, second, and third fin structures;
depositing a dielectric layer between the first and second fin structures and between the second and third fin structures, wherein a seam is formed in the dielectric layer between the first and second fin structures;
removing portions of the dielectric layer between the first and second fin structures to expose the seam and between the second and third fin structures to expose the liner layer;
depositing an insulation material to embed the first, second, and third fin structures, wherein the insulation material is in contact with the liner layer between the second and third fin structures, and the seam between the first and second fin structures is filled with the insulation material;
implanting a dopant into the insulation material between the first and second fin structures; and
performing an etch process, wherein the insulation material between the first and second fin structures is etched at a slower rate than the insulation material between the second and third fin structures.

### Claim 11 (depends on 10)

The method of claim 10, wherein the dielectric layer and the insulation material comprise different materials.

### Claim 12 (depends on 11)

The method of claim 11, wherein the dielectric layer comprises SiN, SiC, SiCN, AlOx, or SiOCN, and the insulation material comprises silicon oxide.

### Claim 13 (depends on 10)

The method of claim 10, wherein the liner layer comprises a semiconductor material.

### Claim 14 (depends on 10)

The method of claim 10, wherein the dielectric layer is deposited by atomic layer deposition, and the insulation material is deposited by flowable chemical vapor deposition.

### Claim 15 (depends on 10)

The method of claim 10, wherein a distance between the first and second fin structures is substantially smaller than a distance between the second and third fin structures.

### Claim 16 (depends on 10)

The method of claim 10, wherein each of the first, second, and third fin structures comprises alternating first and second nanostructures.

### Claim 17

A method, comprising:
forming first, second, and third fin structures over a substrate, wherein a first trench having a first width is formed between the first and second fin structures, and a second trench having a second width substantially greater than the first width is formed between the second and third fin structures;
depositing a first dielectric layer in the first and second trenches, wherein a seam is formed in the first dielectric layer in the first trench, and the first dielectric layer is a conformal layer;
removing portions of the first dielectric layer in the first and second trenches, wherein the seam in the first trench is exposed;
depositing a second dielectric layer in the first and second trenches, wherein the seam in the first trench is filled with the second dielectric layer, and a dielectric wall comprising the first and second dielectric layers is formed in the first trench;
removing the first and second dielectric layers in the second trench, wherein a top surface of the dielectric wall is located below a level of a top surface of the first fin structure; and
forming a shallow trench isolation region in the second trench.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
forming a sacrificial gate structure over a portion of the first fin structure, a portion of the second fin structure, and a portion of the dielectric wall;
recessing exposed portions of the first fin structure, exposed portions of the second fins structure, and exposed portions of the dielectric wall;
forming first and second source/drain (S/D) regions from the recessed first and second fins, wherein the first S/D region is separated from the second S/D region by the dielectric wall; and
forming an interlayer dielectric (ILD) layer over the first and second S/D regions.

### Claim 19 (depends on 18)

The method of claim 18, further comprising:
removing the sacrificial gate structure; and
forming a first gate electrode layer over the portion of the first fin structure and a second gate electrode layer over the portion of the second fin structure, wherein the portion of the dielectric wall is under the first and second gate electrode layers.

### Claim 20 (depends on 18)

The method of claim 18, wherein the portion of the dielectric wall separating the first and second S/D regions has a height substantially less than a height of the portion of the dielectric wall under the first and second gate electrode.