# US 2025/0098265 A1 · Semiconductor devices

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- Number: US 2025/0098265 A1
- Document ID: US20250098265A1
- Status: Published application
- Kind: A1
- Application number: 18/636,572
- Filed: 2024-04-16
- Published: 2025-03-20
- Earliest claimed: 2023-09-18
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Dong Hoon Kwon
- Web page: https://patentgrep.com/patent/US20250098265A1

## CPC

- H10D 64/254: {for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/427: {Power or ground buses}
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 20/48: Insulating materials thereof
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- H10W 20/0698: {Local interconnections}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device may include a first substrate, a lower pattern on a first side of the first substrate, a plurality of sheet patterns on the lower pattern and spaced apart from each other in a first direction, a gate electrode which surrounds portions the plurality of sheet patterns, a source/drain pattern which is on one side of the gate electrode and connected to the plurality of sheet patterns, a power rail which is on a second side of the first substrate, a via pattern which extends through the first substrate in the first direction, and is connected to both the power rail and the source/drain pattern, a first dummy pattern on the via pattern, a second substrate on the first dummy pattern, and a second dummy pattern on a third side of the second substrate that faces the first side of the first substrate.

## Claims

### Claim 1

A semiconductor device comprising:
a first substrate which includes a first side and a second side that are opposite from each other in a first direction;
a lower pattern on the first side of the first substrate, the lower pattern extending in a second direction that intersects the first direction;
a plurality of sheet patterns which are spaced apart from each other in the first direction on the lower pattern;
a gate electrode surrounding portions of the plurality of sheet patterns on the first side of the first substrate, the gate electrode extending in a third direction that intersects the first direction and the second direction;
a source/drain pattern which is on a first side of the gate electrode and connected to the plurality of sheet patterns;
a power rail which is on the second side of the first substrate and which extends in the second direction;
a via pattern which extends through the first substrate in the first direction, the via pattern connected to the power rail and to the source/drain pattern;
a first dummy pattern that includes an insulating material on the via pattern;
a second substrate which includes, on the first dummy pattern, a third side that faces the first side, and a fourth side opposite from the third side in the first direction; and
a second dummy pattern on the third side of the second substrate, the second dummy pattern including an insulating material,
wherein the first dummy pattern and the second dummy pattern overlap each other in the first direction.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first dummy pattern and the second dummy pattern include the same material.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first dummy pattern and the second dummy pattern include different materials from each other.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the first dummy pattern includes a first sub-pattern and a second sub-pattern, and
wherein a depth of the first sub-pattern in the first direction is different from a depth of the second sub-pattern in the first direction.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the second dummy pattern includes a third sub-pattern and a fourth sub-pattern, and
wherein a depth of the third sub-pattern in the first direction is different from a depth of the fourth sub-pattern in the first direction.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the depth of the first sub-pattern in the first direction is smaller than the depth of the second sub-pattern in the first direction,
wherein the depth of the third sub-pattern in the first direction is smaller than the depth of the fourth sub-pattern in the first direction,
wherein the first sub-pattern and the third sub-pattern overlap in the first direction, and
wherein the second sub-pattern and the fourth sub-pattern overlap in the first direction.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein each of the first dummy pattern and the second dummy pattern has at least one of a circular shape, a square shape, and a rod shape when viewed in a plan view.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, further comprising a source/drain contact on the source/drain pattern,
wherein the via pattern is directly connected to the source/drain contact.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the via pattern extends through the lower pattern and is directly connected to the source/drain pattern.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, further comprising:
a field insulating film on the first side of the first substrate, the field insulating film covering a side wall of the lower pattern; and
a source/drain contact on the source/drain pattern,
wherein the via pattern extends through the field insulation film, and
wherein an upper side of the via pattern is coplanar with an upper side of the source/drain contact.

### Claim 11

A semiconductor device comprising:
a first substrate including a first side and a second side that are opposite to each other in a first direction;
a lower pattern on the first side of the first substrate, the lower pattern extending in a second direction that intersects the first direction;
a field insulating film on the first side of the first substrate and on a side wall of the lower pattern;
a plurality of sheet patterns which are spaced apart from each other in the first direction on the lower pattern;
a gate electrode surrounding portions of the plurality of sheet patterns on the first side of the first substrate, the gate electrode extending in a third direction;
a source/drain pattern which is on one side of the gate electrode and connected to the plurality of sheet patterns;
a power rail on the second side of the first substrate and extending in the second direction;
a via pattern which extends through the first substrate and the field insulating film in the first direction, and is connected to each of the power rail and the source/drain pattern;
a first insulating film on the first side of the first substrate;
a first dummy pattern arranged in the first insulating film, the first dummy pattern including an insulating material that is a different material than a material included in the first insulating film;
a second substrate which includes, on the first dummy pattern, a third side that faces the first side, and a fourth side that is opposite to the third side in the first direction;
a second insulating film on the third side of the second substrate; and
a second dummy pattern in the second insulating film and including an insulating material that is different from a material included in the second insulating film,
wherein the first dummy pattern and the second dummy pattern are offset in the first direction.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the first dummy pattern and the second dummy pattern include the same material.

### Claim 13 (depends on 11)

The semiconductor device of claim 11, wherein the first dummy pattern and the second dummy pattern include different materials from each other.

### Claim 14 (depends on 11)

The semiconductor device of claim 11, wherein the first dummy pattern includes a first sub-pattern and a second sub-pattern, and
wherein a depth of the first sub-pattern in the first direction is smaller than a depth of the second sub-pattern in the first direction.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the second dummy pattern includes a third sub-pattern and a fourth sub-pattern, and
wherein a depth of the third sub-pattern in the first direction is smaller from a depth of the fourth sub-pattern in the first direction.

### Claim 16 (depends on 11)

The semiconductor device of claim 11, wherein a depth of the first dummy pattern in the first direction is smaller than a height of the first insulating film in the first direction.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein a depth of the second dummy pattern in the first direction is smaller than a height of the second insulating film in the first direction.

### Claim 18 (depends on 11)

The semiconductor device of claim 11, wherein the first insulating film and the second insulating film include the same material.

### Claim 19 (depends on 11)

The semiconductor device of claim 11, wherein the first insulating film includes the same material as the second dummy pattern, and
wherein the second insulating film includes the same material as the first dummy pattern.

### Claim 20

A semiconductor device comprising:
a first substrate which includes a first side and a second side that are opposite to each other in a first direction;
a plurality of lower patterns which extend in a second direction on the first side of the first substrate, and are spaced apart from each other in a third direction;
a field insulating film on side walls of the plurality of lower patterns, on the first side of the first substrate;
a plurality of sheet patterns which are spaced apart from each other in the first direction, on the plurality of lower patterns;
a plurality of gate electrodes which surround portions of the plurality of sheet patterns on the first side of the first substrate, extend in the third direction, and are spaced apart from each other in the second direction;
a plurality of source/drain patterns which are between the plurality of gate electrodes, each of the plurality of source/drain patterns connected to at least one of the plurality of sheet patterns;
a plurality of source/drain contacts which are on each of the plurality of source/drain patterns;
a power rail which is on the second side of the first substrate and which extends in the second direction;
a plurality of via patterns which extend through the first substrate and the field insulating film in the first direction, and are connected to each of the power rail and the plurality of source/drain patterns;
a first insulating film on the first side of the first substrate;
a first dummy pattern which extends through the first insulating film, and includes an insulating material that is different from a material included in the first insulating film;
a first adhesive film which covers the first insulating film and the first dummy pattern;
a second substrate which includes, on the first dummy pattern, a third side that faces the first side, and a fourth side opposite to the third side in the first direction;
a second insulating film on the third side of the second substrate;
a second dummy pattern which extends through the second insulating film, and includes an insulating material that is a different material from a material included in the second insulating film; and
a second adhesive film which covers the second insulating film and the second dummy pattern,
wherein the first adhesive film is bonded to the second adhesive film,
wherein each of the first dummy pattern and the second dummy pattern has at least one of a circular shape, a quadrangular shape, and a bar shape when viewed in a plan view,
wherein the first dummy pattern and the second dummy pattern overlap each other in the first direction,
wherein the first insulating film and the second insulating film include the same material, and
wherein the first dummy pattern and the second dummy pattern include the same material.