# US 2025/0098264 A1 · Semiconductor device

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- Number: US 2025/0098264 A1
- Document ID: US20250098264A1
- Status: Published application
- Kind: A1
- Application number: 18/604,031
- Filed: 2024-03-13
- Published: 2025-03-20
- Earliest claimed: 2023-09-14
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Sangcheol NA; Beomjin KIM; Yoolim AHN; Kyoungwoo LEE; Minseung LEE; Hyeryeong LEE; Keun Hwi CHO; Seungseok HA
- Web page: https://patentgrep.com/patent/US20250098264A1

## CPC

- H10D 64/254: {for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes an insulating layer including a first surface, a second surface, and an element isolation trench, an insulating pattern on the first surface of the insulating layer, an active pattern on the insulating pattern and including channel patterns, a source/drain pattern on at least one side of the active pattern, a lower wiring structure on the second surface of the insulating layer, and a through-via that extending in the insulating layer and connecting the source/drain pattern and the lower wiring structure, where the insulating pattern may include a first portion between the insulating layer and the active pattern, a second portion surrounding at least a portion of the through-via, and a third portion on a bottom surface of the element isolation trench.

## Claims

### Claim 1

A semiconductor device comprising:
an insulating layer comprising:
a first surface;
a second surface; and
an element isolation trench;
an insulating pattern on the first surface of the insulating layer;
an active pattern on the insulating pattern and comprising a channel pattern;
a source/drain pattern on at least one side of the active pattern;
a lower wiring structure on the second surface of the insulating layer; and
a through-via that extending in the insulating layer and connecting the source/drain pattern and the lower wiring structure,
wherein the insulating pattern comprises:
a first portion between the insulating layer and the active pattern;
a second portion surrounding at least a portion of the through-via; and
a third portion on a bottom surface of the element isolation trench.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the third portion of the insulating pattern is on an inner wall of the element isolation trench, and
wherein a length of the second portion of the insulating pattern in the thickness direction of the insulating layer is smaller than a length of the third portion of the insulating pattern in the thickness direction of the insulating layer.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein a lower surface of the first portion of the insulating pattern is farther from the second surface of the insulating layer than a lower surface of the source/drain pattern is from the second surface of the insulating layer.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the second portion of the insulating pattern contacts at least a portion of a side surface of the source/drain pattern.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the through-via comprises:
a first via portion at least partially surrounded by the second portion of the insulating pattern; and
a second via portion between the first via portion and the lower wiring structure.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein a width of the second via portion is greater than a width of the first via portion.

### Claim 7 (depends on 5)

The semiconductor device of claim 5, wherein at least a portion of the second portion of the insulating pattern extends over the second via portion in a direction parallel with the second surface of the insulating layer, and
wherein at least another portion of the second portion of the insulating pattern does not extend over the second via portion in the direction parallel with the second surface of the insulating layer.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, further comprising:
a gate structure on the insulating pattern and at least partially surrounding the channel pattern,
wherein the active pattern further comprises a lower pattern between the first portion of the insulating pattern and the gate structure.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, further comprising:
a dummy source/drain pattern below the source/drain pattern,
wherein the insulating pattern further comprises a fourth portion at least partially surrounding the dummy source/drain pattern.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein an upper surface of the dummy source/drain pattern is closer to the second surface of the insulating layer than a lower surface of the gate structure is from the second surface of the insulating layer.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, further comprising:
a gate structure on the insulating pattern and at least partially surrounding the channel pattern,
wherein the first portion of the insulating pattern contacts the gate structure.

### Claim 12 (depends on 1)

The semiconductor device of claim 1, wherein the insulating pattern comprises a material having etch selectivity to the insulating layer.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the insulating pattern comprises at least one of SiN, SiON, SiCN, SiOC, SiOCN, and metal oxides.

### Claim 14 (depends on 1)

The semiconductor device of claim 1, wherein the insulating pattern further comprises:
an outer insulating pattern contacting the insulating layer; and
an inner insulating pattern on the outer insulating pattern, and wherein the inner insulating pattern comprises at least one of SiN, SiON, SiCN, SiOC, SiOCN, AlN, and Al2O3.

### Claim 15

A semiconductor device comprising:
an insulating layer comprising a first surface and a second surface;
an insulating pattern on the first surface of the insulating layer;
an active pattern on the insulating pattern and comprising a channel pattern;
a source/drain pattern on at least one side of the active pattern;
a dummy source/drain pattern extending in at least a portion of the insulating pattern and positioned below the source/drain pattern;
a lower wiring structure below the second surface of the insulating layer; and
a through-via extending in the insulating layer and connecting the source/drain pattern and the lower wiring structure,
wherein the insulating pattern comprises:
a first portion between the insulating layer and the active pattern;
a second portion surrounding at least a portion of the through-via; and
a fourth portion at least partially surrounding the dummy source/drain pattern.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein a length of the fourth portion of the insulating pattern in the thickness direction of the insulating layer is greater than a length of the second portion of the insulating pattern in the thickness direction of the insulating layer.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein the second portion of the insulating pattern contacts at least a portion of a side surface of the source/drain pattern.

### Claim 18 (depends on 15)

The semiconductor device of claim 15, wherein a lower surface of the first portion of the insulating pattern is farther from the second surface of the insulating layer than a lower surface of the source/drain pattern is from the second surface of the insulating layer.

### Claim 19

A semiconductor device comprising:
an insulating layer comprising:
a first surface;
a second surface facing; and
an element isolation trench;
an insulating pattern on the first surface of the insulating layer;
an active pattern on the insulating pattern and comprising a channel pattern;
a source/drain pattern on at least one side of the active pattern;
a dummy source/drain pattern extending in at least a portion of the insulating pattern and below the source/drain pattern;
a gate electrode on the insulating pattern and at least partially surrounding the channel pattern;
a lower wiring structure below the second surface of the insulating layer; and
a through-via extending in the insulating layer and connecting the source/drain pattern and the lower wiring structure,
wherein the insulating pattern comprises:
a first portion between the insulating layer and the gate electrodes;
a second portion surrounding at least a portion of the through-via;
a third portion on inner walls and bottom surfaces of the element isolation trench; and
a fourth portion at least partially surrounding the dummy source/drain pattern, and
wherein the through-via comprises:
a first via portion at least partially surrounded by the second portion of the insulating pattern; and
a second via portion between the first via portion and the lower wiring structure.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein a length of the second portion of the insulating pattern in the thickness direction of the insulating layer is smaller than a length of the third portion of the insulating pattern in the thickness direction of the insulating layer.