# US 2025/0098259 A1 · Semiconductor device structure and methods of forming the same

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- Number: US 2025/0098259 A1
- Document ID: US20250098259A1
- Status: Published application
- Kind: A1
- Application number: 18/368,014
- Filed: 2023-09-14
- Published: 2025-03-20
- Earliest claimed: 2023-09-14
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Ya-Wen CHIU; Yi-Hua CHENG; Szu-Ying CHEN; Zheng-Yang PAN
- Web page: https://patentgrep.com/patent/US20250098259A1

## CPC

- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The method includes forming a first fin structure and a second fin structure from a substrate, depositing a first conformal layer over the first and second fin structures and between the first and second fin structures, depositing a second conformal layer on the first conformal layer, depositing a third conformal layer on the second conformal layer, depositing a fourth conformal layer on the third conformal layer, depositing a first insulating material on the fourth conformal layer between the first and second fin structures, and depositing a second insulating material on the first insulating material. The first and second fin structures are embedded by the second insulating material. The method further includes removing portions of the second insulating material and the first, second, third, and fourth conformal layers to expose the first and second fin structures.

## Claims

### Claim 1

A method, comprising:
forming a first fin structure and a second fin structure from a substrate;
depositing a first conformal layer over the first and second fin structures and between the first and second fin structures;
depositing a second conformal layer on the first conformal layer;
depositing a third conformal layer on the second conformal layer;
depositing a fourth conformal layer on the third conformal layer;
depositing a first insulating material on the fourth conformal layer between the first and second fin structures;
depositing a second insulating material on the first insulating material, wherein the first and second fin structures are embedded by the second insulating material; and
removing portions of the second insulating material and the first, second, third, and fourth conformal layers to expose the first and second fin structures.

### Claim 2 (depends on 1)

The method of claim 1, wherein each of the first and second fin structures comprises alternating first and second semiconductor layers disposed on a well portion.

### Claim 3 (depends on 2)

The method of claim 2, wherein the well portion has a first top surface, and top surfaces of the second insulating material, the first conformal layer, the second conformal layer, the third conformal layer, and the fourth conformal layer are located at a level at or below the first top surface.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first and second insulating materials have a total thickness, and the second insulating material has a first thickness that is about 15 percent to about 45 percent of the total thickness.

### Claim 5 (depends on 4)

The method of claim 4, wherein the first insulating material has a second thickness greater than the first thickness.

### Claim 6 (depends on 4)

The method of claim 4, wherein the first thickness ranges from about 50 nm to about 150 nm, and the second thickness ranges from about 200 nm to about 300 nm.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
forming a sacrificial gate stack on a first portion of the first and second fin structures; and
recessing a second portion of the first and second fin structures, wherein the first, second, third, fourth conformal layers, and the first insulating material are recessed, and the second insulating material is removed during the recessing the second portion of the first and second fin structures.

### Claim 8

A method, comprising:
forming a first fin structure and a second fin structure from a substrate;
depositing a first conformal layer over the first and second fin structures and between the first and second fin structures;
depositing a second conformal layer on the first conformal layer;
depositing a third conformal layer on the second conformal layer;
depositing a fourth conformal layer on the third conformal layer;
depositing a first insulating material on the fourth conformal layer between the first and second fin structures;
performing a first anneal process, wherein the fourth conformal layer expands during the first anneal process and causes densities of the first, second, and third conformal layers to increase;
depositing a second insulating material on the first insulating material, wherein the first and second fin structures are embedded by the second insulating material;
removing portions of the second insulating material and the first, second, third, and fourth conformal layers to expose tops of the first and second fin structures;
performing a second anneal process; and
recessing the second insulating material and the first, second, third, and fourth conformal layers.

### Claim 9 (depends on 8)

The method of claim 8, wherein the fourth conformal layer comprises a semiconductor.

### Claim 10 (depends on 9)

The method of claim 9, wherein fourth conformal layer is oxidized by the first anneal process.

### Claim 11 (depends on 8)

The method of claim 8, wherein the third conformal layer comprises carbon, and the carbon diffuses into the first insulating material during the first anneal process.

### Claim 12 (depends on 11)

The method of claim 11, wherein the second conformal layer comprises nitrogen, and the nitrogen diffuses into the first insulating material during the first anneal process.

### Claim 13 (depends on 8)

The method of claim 8, further comprising:
forming a sacrificial gate stack on a first portion of the first and second fin structures;
forming a gate spacer;
recessing a second portion of the first and second fin structures, wherein the gate spacer, the first, second, third, fourth conformal layers, and the first insulating material are recessed, and the second insulating material is removed during the recessing the second portion of the first and second fin structures.

### Claim 14 (depends on 13)

The method of claim 13, wherein the gate spacer is in contact with the first conformal layer.

### Claim 15 (depends on 8)

The method of claim 8, further comprising depositing a semiconductor layer over the first and second fin structures and between the first and second fin structures, wherein the first conformal layer is deposited on the semiconductor layer.

### Claim 16 (depends on 15)

The method of claim 15, wherein the semiconductor layer is oxidized during the first anneal process.

### Claim 17

A semiconductor device structure, comprising:
a first source/drain region disposed over a substrate;
a first well portion disposed below the first source/drain region;
a second source/drain region disposed over the substrate;
a second well portion disposed below the second source/drain region; and
an insulating structure disposed between the first and second well portions, the insulating structure comprising:
an insulating material having a first height;
a first conformal layer in contact with the insulating material, wherein the first conformal layer has a second height different from the first height;
a second conformal layer in contact with the first conformal layer, wherein the second conformal layer has a third height different from the second height; and
a third conformal layer in contact with the second conformal layer, wherein the third conformal layer has a fourth height different from the third height.

### Claim 18 (depends on 17)

The semiconductor device structure of claim 17, further comprising a fourth conformal layer in contact with the third conformal layer, wherein the fourth conformal layer has a fifth height different from the third height.

### Claim 19 (depends on 17)

The semiconductor device structure of claim 17, wherein the first, second, third, and fourth conformal layers each has a thickness that decreases in a direction away from the substrate.

### Claim 20 (depends on 17)

The semiconductor device structure of claim 17, wherein the first conformal layer comprises an oxide, the second conformal layer comprises carbon, and the third conformal layer comprises nitrogen.