# US 2025/0098252 A1 · Semiconductor device and method for fabricating the same

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- Number: US 2025/0098252 A1
- Document ID: US20250098252A1
- Status: Published application
- Kind: A1
- Application number: 18/379,667
- Filed: 2023-10-13
- Published: 2025-03-20
- Earliest claimed: 2023-09-20
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Ke-Ting Chen; Ching-Ling Lin; Wen-An Liang; Chia-Fu Hsu
- Web page: https://patentgrep.com/patent/US20250098252A1

## CPC

- H10D 64/01: Manufacture or treatment
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D 64/511: {for IGFETs}
- H10P 50/73: {using masks for insulating materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a contact etch stop layer (CESL) adjacent to the metal gate, and an interlayer dielectric (ILD) layer around the gate structure, performing a first etching process to remove the ILD layer, performing a second etching process to remove the CESL for forming a first contact hole, and then forming a first contact plug in the first contact hole. Preferably, a width of the first contact plug adjacent to the CESL is less than a width of the first contact plug under the CESL.

## Claims

### Claim 1

A method for fabricating a semiconductor device, comprising:
forming a metal gate on a substrate, a contact etch stop layer (CESL) adjacent to the metal gate, and an interlayer dielectric (ILD) layer around the gate structure;
performing a first etching process to remove the ILD layer; and
performing a second etching process to remove the CESL for forming a first contact hole.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming a gate structure on a substrate;
forming a source/drain region adjacent to the gate structure;
forming the CESL adjacent to the gate structure;
forming the ILD layer around the CESL;
performing a replacement metal gate (RMG) process to transform the gate structure into the metal gate;
forming a first hard mask on the metal gate;
forming a second hard mask on the first hard mask and the ILD layer;
performing the first etching process to remove the second hard mask and the ILD layer;
performing the second etching process to remove the CESL and the first hard mask forming the first contact hole and a second contact hole; and
forming a first contact plug in the first contact hole and a second contact plug in the second contact hole.

### Claim 3 (depends on 2)

The method of claim 2, wherein a width of the first contact plug adjacent to the CESL is less than a width of the first contact plug under the CESL.

### Claim 4 (depends on 2)

The method of claim 2, wherein a width of the first contact plug adjacent to the CESL is less than a width of the first contact plug above the CESL.

### Claim 5 (depends on 2)

The method of claim 2, wherein a sidewall of the first contact plug comprises a non-planar surface.

### Claim 6 (depends on 2)

The method of claim 2, wherein the second contact plug between the first hard mask comprises:
a first width closer to the metal gate; and
a second width closer to the second hard mask.

### Claim 7 (depends on 6)

The method of claim 6, wherein the second width is less than the first width.

### Claim 8 (depends on 2)

The method of claim 2, wherein a sidewall of the second contact plug comprises a non-planar surface.

### Claim 9

A semiconductor device, comprising:
a metal gate on a substrate;
a contact etch stop layer (CESL) adjacent to the metal gate;
an interlayer dielectric (ILD) layer around the CESL; and
a first contact plug in the ILD layer, wherein a width of the first contact plug adjacent to the CESL is less than a width of the first contact plug under the CESL.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein a width of the first contact plug adjacent to the CESL is less than a width of the first contact plug above the CESL.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein a sidewall of the first contact plug comprises a non-planar surface.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, further comprising:
a first hard mask on the metal gate, wherein top surfaces of the first hard mask and the ILD layer are coplanar;
a second hard mask on the first hard mask; and
a second contact plug on the metal gate.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the second contact plug between the first hard mask comprises:
a first width closer to the metal gate; and
a second width closer to the second hard mask.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the second width is less than the first width.

### Claim 15 (depends on 12)

The semiconductor device of claim 12, wherein a sidewall of the second contact plug comprises a non-planar surface.