# US 2025/0098249 A1 · Mitigating proximity effects of deep trench vias

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- Number: US 2025/0098249 A1
- Document ID: US20250098249A1
- Status: Published application
- Kind: A1
- Application number: 18/467,859
- Filed: 2023-09-15
- Published: 2025-03-20
- Earliest claimed: 2023-09-15
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Avijit Barik; Tao Chu; Minwoo Jang; Tofizur RAHMAN; Conor P. Puls; Ariana E. Bondoc; Diane Lancaster; Chi-Hing Choi; Derek Keefer
- Web page: https://patentgrep.com/patent/US20250098249A1

## CPC

- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/01: Manufacture or treatment
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0238: {comprising etching via holes through pads or through electrodes}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/212: {Top-view shapes or dispositions, e.g. top-view layouts of the vias}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Disclosed herein are IC structures and devices that aim to mitigate proximity effects of deep trench vias. An example IC structure may include a device region having a first face and a second face, the second face being opposite the first face, and further include a conductive via extending between the first face and the second face, wherein the conductive via includes an electrically conductive material, and wherein a concentration of titanium at sidewalls of the conductive via is below about 1015 atoms per cubic centimeter.

## Claims

### Claim 1

An integrated circuit (IC) structure, comprising:
a transistor comprising a region of a doped semiconductor material, wherein the region is either a source region or a drain region of the transistor; and
a contact structure coupled to the region, the contact structure comprising an interface material and a fill material, wherein, within the contact structure, the interface material is limited to an area between the region and the fill material.

### Claim 2 (depends on 1)

The IC structure according to claim 1, wherein the interface material is limited to the area between the region and the fill material by being at a bottom of the contact structure and being substantially absent from sidewalls of the contact structure.

### Claim 3 (depends on 1)

The IC structure according to claim 1, further comprising a device region, wherein:
the transistor and the contact structure to the region are within the device region,
the device region has a first face and a second face, the second face being opposite the first face,
the device region further includes a conductive via extending between the first face and the second face, and
the interface material is absent from sidewalls of the conductive via or a concentration of the interface material at the sidewalls of the conductive via is below about 1015 atoms per cubic centimeter.

### Claim 4 (depends on 3)

The IC structure according to claim 3, wherein the conductive via includes an electrically conductive fill material and wherein sidewalls of the conductive via are surrounded by an insulator material.

### Claim 5 (depends on 4)

The IC structure according to claim 4, wherein the electrically conductive fill material is in contact with the insulator material.

### Claim 6 (depends on 4)

The IC structure according to claim 4, wherein the conductive via further includes a liner material, and wherein the electrically conductive fill material is in contact with the liner material, and the liner material is in contact with the insulator material.

### Claim 7 (depends on 6)

The IC structure according to claim 6, wherein the liner material includes carbon or nitrogen.

### Claim 8 (depends on 6)

The IC structure according to claim 6, wherein the liner material either excludes the interface material or a concentration of the interface material within the liner material is below about 1015 atoms per cubic centimeter.

### Claim 9 (depends on 4)

The IC structure according to claim 4, wherein the electrically conductive fill material includes tungsten.

### Claim 10 (depends on 1)

The IC structure according to claim 1, wherein the interface material is titanium.

### Claim 11 (depends on 1)

The IC structure according to claim 1, wherein the doped semiconductor material includes silicon, and the interface material includes titanium and silicon.

### Claim 12 (depends on 1)

The IC structure according to claim 1, wherein a thickness of the interface material in the area between the region and the fill material is below about 5 nanometers.

### Claim 13 (depends on 1)

The IC structure according to claim 1, wherein, within the contact structure, one side of the interface material is in contact with the fill material and another side of the interface material is in contact with the doped semiconductor material.

### Claim 14

An integrated circuit (IC) structure, comprising:
a device region having a first face and a second face, the second face being opposite the first face; and
a conductive via extending between the first face and the second face, wherein the conductive via includes an electrically conductive material, and wherein a concentration of titanium at sidewalls of the conductive via is below about 1015 atoms per cubic centimeter.

### Claim 15 (depends on 14)

The IC structure according to claim 14, wherein the device region includes:
a transistor, and
a contact coupled to a source region of the transistor, wherein a portion of the contact closest to the source region includes an interface material, and the interface material includes titanium.

### Claim 16 (depends on 15)

The IC structure according to claim 15, wherein titanium is substantially absent from sidewalls of the contact.

### Claim 17 (depends on 14)

The IC structure according to claim 14, further comprising a plurality of first interconnects at the first face of the device region, and a plurality of second interconnects at the second face of the device region, wherein:
the conductive via is electrically connected to at least one of the first interconnects or at least one of the second interconnects,
in a cross-section substantially perpendicular to the device region, an individual one of the conductive via, the at least one of the first interconnects, and the at least one of the second interconnects has a trapezoidal shape having a first side and a second side, wherein the first side is substantially parallel to the second side and shorter than the second side,
for the trapezoidal shape of the at least one of the first interconnects and the trapezoidal shape of the conductive via, the first side is closer to the second interconnects than the second side, and
for the trapezoidal shape of the at least one of the second interconnects, the first side is closer to the device region than the second side.

### Claim 18

A method of fabricating an integrated circuit (IC) structure, the method comprising:
providing a channel material over a portion of a support;
forming a source region of a transistor in the channel material;
providing a further material over the source region;
forming an opening extending through the further material to expose a portion of the source region;
performing selective deposition to deposit titanium at a bottom of the opening without substantially depositing titanium on sidewalls of the opening; and
after performing selective deposition, filling the opening with an electrically conductive material.

### Claim 19 (depends on 18)

The method according to claim 18, wherein the portion of the support is a first portion, the opening is a first opening, the electrically conductive material is a first electrically conductive material, and the method further includes:
providing an insulator material over a second portion of the support;
forming a second opening extending into the insulator material;
performing selective deposition to deposit titanium at a bottom of the second opening without substantially depositing titanium on sidewalls of the second opening; and
after performing selective deposition to deposit titanium at the bottom of the second opening, filling the second opening with a second electrically conductive material.

### Claim 20 (depends on 19)

The method according to claim 19, wherein selective deposition to deposit titanium at the bottom of the first opening is performed substantially simultaneously with performing selective deposition to deposit titanium at the bottom of the second opening.