# US 2025/0098245 A1 · Source/drain regions for nanosheet devices

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- Number: US 2025/0098245 A1
- Document ID: US20250098245A1
- Status: Published application
- Kind: A1
- Application number: 18/470,669
- Filed: 2023-09-20
- Published: 2025-03-20
- Earliest claimed: 2023-09-20
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Sagarika Mukesh; Alexander Reznicek; Tao Li; Ruilong Xie
- Web page: https://patentgrep.com/patent/US20250098245A1

## CPC

- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/01: Manufacture or treatment
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3466: {Crystal orientation}
- H10W 20/427: {Power or ground buses}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device comprises a stacked structure, the stacked structure comprising a plurality of gate structures alternately stacked with a plurality of channel layers. At least one epitaxial source/drain region disposed on a side of the stacked structure, and the stacked structure is disposed on at least one dielectric layer. A portion of the at least one epitaxial source/drain region is disposed in the at least one dielectric layer.

## Claims

### Claim 1

A semiconductor device comprising:
a stacked structure comprising a plurality of gate structures alternately stacked with a plurality of channel layers; and
at least one epitaxial source/drain region disposed on a side of the stacked structure;
wherein the stacked structure is disposed on at least one dielectric layer; and
wherein a portion of the at least one epitaxial source/drain region is disposed in the at least one dielectric layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising an additional dielectric layer on the at least one dielectric layer, wherein the stacked structure is further disposed on the additional dielectric layer, and the at least one epitaxial source/drain region is disposed through the additional dielectric layer into the at least one dielectric layer.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein a shallow trench isolation region is disposed around one or more sides of the portion of the at least one epitaxial source/drain region.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further comprising a source/drain contact disposed in the at least one dielectric layer and on the portion of the at least one epitaxial source/drain region.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the source/drain contact is connected to a backside power delivery network.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein side surfaces of respective ones of the plurality of channel layers contact a side surface of the at least one epitaxial source/drain region.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein at least a portion of the side surfaces of the respective ones of the plurality of channel layers comprise arsenic.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the at least one epitaxial source/drain region is disposed in the at least one dielectric layer at a depth below a lowermost surface of the stacked structure.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, further comprising a source/drain contact disposed on a surface of an additional portion of the at least one epitaxial source/drain region located opposite to the portion of the at least one epitaxial source/drain region.

### Claim 10

A semiconductor device comprising:
a first nanosheet structure comprising a first plurality of gate structures alternately stacked with a first plurality of channel layers;
a second nanosheet structure comprising a second plurality of gate structures alternately stacked with a second plurality of channel layers; and
at least one epitaxial source/drain region disposed between the first and second nanosheet structures;
wherein the first and second nanosheet structures are disposed on at least one dielectric layer; and
wherein a portion of the at least one epitaxial source/drain region is disposed in the at least one dielectric layer.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, further comprising an additional dielectric layer on the at least one dielectric layer, wherein the first and second nanosheet structures are further disposed on the additional dielectric layer, and the at least one epitaxial source/drain region is disposed through the additional dielectric layer into the at least one dielectric layer.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, further comprising a source/drain contact disposed in the at least one dielectric layer and on the portion of the at least one epitaxial source/drain region.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the source/drain contact is connected to a backside power delivery network.

### Claim 14 (depends on 10)

The semiconductor device of claim 10, wherein side surfaces of respective ones of the plurality of first and second channel layers contact side surfaces of the at least one epitaxial source/drain region.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein at least a portion of the side surfaces of the respective ones of the plurality of first and second channel layers comprise arsenic.

### Claim 16

A method comprising:
forming a stacked structure comprising a plurality of sacrificial semiconductor layers alternately stacked with a plurality of channel layers, wherein the stacked structure is formed on a semiconductor layer comprising a surface with a designated crystal orientation; and
growing at least one epitaxial source/drain region on a side of the stacked structure from an exposed portion of the semiconductor layer in a bottom-up epitaxial growth process.

### Claim 17 (depends on 16)

The method of claim 16, wherein the semiconductor layer comprises silicon germanium, and the designated crystal orientation comprises a <100> orientation.

### Claim 18 (depends on 16)

The method of claim 16, further comprising exposing side surfaces of respective ones of the plurality of channel layers to arsine prior to growing the at least one epitaxial source/drain region.

### Claim 19 (depends on 16)

The method of claim 16, further comprising removing part of the semiconductor layer to form a trench in the semiconductor layer, wherein the trench comprises the exposed portion of the semiconductor layer from which the at least one epitaxial source/drain region is grown, and extends to a depth below and spaced apart from a lowermost surface of the stacked structure.

### Claim 20 (depends on 19)

The method of claim 19, wherein a dielectric layer is formed on the semiconductor layer, and the method further comprises removing a portion of the dielectric layer to expose the part of the semiconductor layer to be removed to form the trench.