# US 2025/0098232 A1 · Semiconductor device structure and methods of forming the same

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- Number: US 2025/0098232 A1
- Document ID: US20250098232A1
- Status: Published application
- Kind: A1
- Application number: 18/421,312
- Filed: 2024-01-24
- Published: 2025-03-20
- Earliest claimed: 2023-09-14
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Tzu-Ging LIN
- Web page: https://patentgrep.com/patent/US20250098232A1

## CPC

- H10D 62/102: {Constructional design considerations for preventing surface leakage or controlling electric field concentration}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/834: {comprising FinFETs}
- H10D 89/10: Integrated device layouts
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Embodiments of present disclosure relates to forming isolation structures in gate structures to prevent current leakage through source/drain regions (EPI), transistors, and silicon substrate. The isolation structures may be formed in the gate structure prior to or after the replacement gate sequence.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor substrate;
a fin structure on the semiconductor substrate and extending along a first direction;
a plurality of gate structures across the fin structure along a second direction;
a plurality of source/drain regions over the fin structure and between the plurality of gate structures;
a first isolation structure formed in a first gate structure of the plurality of gate structures, wherein the first isolation structure has a first width along the first direction; and
a second isolation structure formed in a second gate structure of the plurality of the gate structures, wherein the second isolation structure has a second width along the first direction, the first gate structure is positioned immediately next to the second gate structure, and the first width is greater than the second width.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the plurality of gate structures are evenly distributed along the first direction at a gate pitch.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the first width is greater than 0.5 times of the gate pitch.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the first isolation structure is a first distance away from the second isolation structure along the first direction, and the first distance is greater than 0.5 times of the gate pitch.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the first isolation structure cuts through the fin structure and extends into the semiconductor substrate for a first depth, the second isolation structure cuts through the fin structure and extends into the semiconductor substrate for a second depth, and the first depth is greater than the second depth.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the fin structure includes a single channel.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the fin structure includes two or more channels.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, further comprising a third isolation structure disposed in a third gate structure of the plurality of gate structures, wherein the third gate structure is disposed immediately next to the first gate structure, and the third isolation structure has a third width less than the first width.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, further comprising a third isolation structure disposed in a third gate structure of the plurality of gate structures, wherein the third gate structure is disposed immediately next to the second gate structure, and the third isolation structure has a third width greater than the second width.

### Claim 10

A semiconductor device, comprising:
a semiconductor substrate;
a plurality of fin structures on the semiconductor substrate and extending along a first direction;
a gate structure disposed across the plurality of fin structures and extending along a second direction; and
an isolation structure disposed in the gate structure, wherein the isolation structure comprises:
a first segment having a first width; and
a second segment having a second width, wherein the first width is greater than the second width.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the first segment cuts into a first fin structure of the plurality of fin structures, and the second segment cuts into a second fin structure of the plurality of fin structures.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the first segment is connected to the second segment.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the first segment extends into the semiconductor substrate for a first depth, the second segment extends into the semiconductor substrate for a second depth, and the first depth is greater than the second depth.

### Claim 14 (depends on 11)

The semiconductor device of claim 11, further comprising:
a second gate structure disposed next to the gate structure;
a second isolation structure disposed in the second gate structure, wherein the second isolation structure cuts into the second fin structure, the second isolation structure has a third width, and the third width is greater than the second width.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the first isolation structure further comprises:
a third segment cutting into a third fin structure of the plurality of fin structures, wherein the third segment and the first segment are connected to two ends of the second segment, the third segment has a fourth width, and the fourth width is greater than the second width.

### Claim 16

A method comprising:
forming a plurality of fin structures on a substrate along a first direction;
forming a plurality of gate structures across the plurality of fin structures;
depositing a mask layer over the plurality of gate structures;
forming a pattern in the mask layer, wherein the pattern comprises:
a first opening in align with a first gate structure of the plurality of gate structures; and
a second opening in align with the second gate structure of the plurality of gate structures, wherein the first gate structures and the second gate structure are immediately next to each other, the first opening has a first width along the first direction, the second opening has a second width along the first direction, and the first width is greater than the second width;
forming a first isolation opening and a second isolation opening using the pattern in the mask layer; and
depositing a dielectric layer to fill the first isolation opening and the second isolation opening.

### Claim 17 (depends on 16)

The method of claim 16, wherein forming the first isolation opening and the second isolation opening comprises:
etching the first and second gate structures to expose the fin structures;
etching through the fin structures and into the substrate, wherein the first isolation opening extends into the substrate for a first depth, the second isolation opening extends into the substrate for a second depth, and the first depth is greater than the second depth.

### Claim 18 (depends on 17)

The method of claim 17, wherein forming the plurality of gate structures comprises forming a plurality of sacrificial gate structures, and further comprising:
after depositing the dielectric layer, performing a replacement process.

### Claim 19 (depends on 16)

The method of claim 16, wherein the pattern further comprises:
a third opening in align with a third gate structure of the plurality of gate structures, wherein the first gate structures and the third gate structure are immediately next to each other, the third opening has a third width along the first direction, and the first width is greater than the third width.

### Claim 20 (depends on 16)

The method of claim 16, wherein the second opening comprises:
a first segment;
a second segment connected to the first segment; and
a third segment connected to the second segment, wherein the first segment and the third segment are wider than the second segment.