# US 2025/0098221 A1 · Complementary field effect transistor (cfet) circuits with vertical routing structures

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2025/0098221 A1
- Document ID: US20250098221A1
- Status: Published application
- Kind: A1
- Application number: 18/470,226
- Filed: 2023-09-19
- Published: 2025-03-20
- Earliest claimed: 2023-09-19
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Shreesh NARASIMHA; Yan SUN
- Web page: https://patentgrep.com/patent/US20250098221A1

## CPC

- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 62/121: {oriented parallel to substrates}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- H10W 20/427: {Power or ground buses}
- H10W 72/00: Interconnections or connectors in packages
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Disclosed are complementary field effect transistor (CFET) circuits with vertical routing structures and methods for making the same. In an aspect, a semiconductor structure comprises a first field effect transistor (FET) of a first charge carrier type, comprising a first source/drain (S/D) region, a second S/D region, and a first gate; a second FET of a second charge carrier type, disposed above the first FET and comprising a third S/D region, a fourth S/D region, and a second gate; a frontside metal (FM) layer disposed above the second FET and comprising an FM conductor extending in an X direction; a backside metal (BM) layer disposed below the first FET and comprising a BM conductor extending in the X direction; and a vertical connector extending in the Z direction, that electrically couples the BM conductor to the FM conductor.

## Claims

### Claim 1

A semiconductor structure, comprising:
at least one complementary field effect transistor (CFET) structure, comprising:
a first field effect transistor (FET) of a first charge carrier type, comprising a first source/drain (S/D) region, a second S/D region, and a first gate;
a second FET of a second charge carrier type, disposed above the first FET in a Z direction and comprising a third S/D region, a fourth S/D region, and a second gate;
a frontside (FS) metal (FM) layer disposed above the second FET in the Z direction and comprising an FM conductor extending in an X direction;
a backside (BS) metal (BM) layer disposed below the first FET in the Z direction and comprising a BM conductor extending in the X direction; and
a vertical connector extending in the Z direction, wherein the vertical connector electrically couples the BM conductor to the FM conductor.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the FM conductor is electrically coupled to at least one of the third S/D region, the fourth S/D region, or the second gate.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein the first gate comprises a first gate-all-around (GAA) structure comprising a first GAA region and wherein the second gate comprises a second GAA structure comprising a second GAA region.

### Claim 4 (depends on 3)

The semiconductor structure of claim 3, wherein:
the first FET comprises a first plurality of nanosheet channels extending in the X direction and spaced apart from each other in the Z direction to from a first vertical stack, each channel electrically coupling the first S/D region to the second S/D region through the first GAA region and being separated from the first GAA region by a first dielectric material; and
the second FET comprises a second plurality of nanosheet channels extending in the X direction and spaced apart from each other in the Z direction to from a second vertical stack disposed above the first vertical stack in the Z direction, each channel electrically coupling the third S/D region to the fourth S/D region through the second GAA region and being separated from the second GAA region by a second dielectric material.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein the vertical connector provides a first supply voltage from the BM conductor to the FM conductor.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein the semiconductor structure comprises a standard cell, wherein the FM conductor is one of a plurality of FM conductors extending in the X direction and spaced apart from each other along a Y direction, and wherein the BM conductor is one of a plurality of BM conductors extending in the X direction and spaced apart from each other along the Y direction.

### Claim 7 (depends on 6)

The semiconductor structure of claim 6, wherein the plurality of FM conductors extending in the X direction consists of four or fewer FM conductors extending in the X direction.

### Claim 8 (depends on 6)

The semiconductor structure of claim 6, wherein the plurality of BM conductors extending in the X direction consists of four or fewer BM conductors extending in the X direction.

### Claim 9 (depends on 6)

The semiconductor structure of claim 6, wherein the plurality of FM conductors extending in the X direction consists of three or fewer FM conductors extending in the X direction.

### Claim 10 (depends on 6)

The semiconductor structure of claim 6, wherein the plurality of BM conductors extending in the X direction consists of three or fewer BM conductors extending in the X direction.

### Claim 11 (depends on 6)

The semiconductor structure of claim 6, further comprising a second vertical connector that electrically couples the second S/D region to the fourth S/D region by direct contact with both the second S/D region and the fourth S/D region.

### Claim 12 (depends on 11)

The semiconductor structure of claim 11, wherein the second vertical connector is electrically coupled to another of the plurality of FM conductors, another of the plurality of BM conductors, or both.

### Claim 13

A semiconductor structure, comprising:
a frontside (FS) metal (FM) layer comprising a plurality of FM conductors extending in an X direction and separated from each other along a Y direction;
a backside (BS) metal (BM) layer disposed below the FM layer in a Z direction and comprising a plurality of BM conductors extending in the X direction and separated from each other along the Y direction; and
a vertical connector extending in the Z direction, wherein the vertical connector electrically couples a first BM conductor of the plurality of BM conductors to a first FM conductor of the plurality of FM conductors.

### Claim 14 (depends on 13)

The semiconductor structure of claim 13, wherein the first BM conductor provides a first supply voltage to the semiconductor structure and wherein the vertical connector provides the first supply voltage from the first BM conductor to the first FM conductor.

### Claim 15 (depends on 14)

The semiconductor structure of claim 14, wherein a second BM conductor of the plurality of BM conductors provides a second supply voltage to the semiconductor structure.

### Claim 16

A method of fabricating a semiconductor structure, the method comprising:
providing at least one complementary field effect transistor (CFET) structure, comprising:
providing a first field effect transistor (FET) of a first charge carrier type, comprising a first S/D region, a second S/D region, and a first gate;
providing a second FET of a second charge carrier type, disposed above the first FET in a Z direction and comprising a third S/D region, a fourth S/D region, and a second gate;
providing a frontside (FS) metal (FM) layer disposed above the second FET in the Z direction and comprising an FM conductor extending in an X direction;
providing a vertical connector extending in the Z direction and being electrically coupled to the FM conductor; and
providing a backside (BS) metal (BM) layer disposed below the first FET in the Z direction and comprising a BM conductor extending in the X direction and being electrically coupled to the vertical connector.

### Claim 17 (depends on 16)

The method of claim 16, further comprising providing an electrical connection from the FM conductor to at least one of the third S/D region, the fourth S/D region, or the second gate.

### Claim 18 (depends on 16)

The method of claim 16, wherein providing the first FET comprises providing a gate-all-around (GAA) FET comprising a first GAA region and wherein providing the second FET comprises providing a GAA FET comprising a second GAA region.

### Claim 19 (depends on 18)

The method of claim 18, wherein:
providing the first FET comprises providing a first plurality of nanosheet channels extending in the X direction and spaced apart from each other in the Z direction to from a first vertical stack, each channel electrically coupling the first S/D region to the second S/D region through the first GAA region and being separated from the first GAA region by a first dielectric material; and
providing the second FET comprises providing a plurality of nanosheet channels extending in the X direction and spaced apart from each other in the Z direction to from a second vertical stack disposed above the first vertical stack in the Z direction, each channel electrically coupling the third S/D region to the fourth S/D region through the second GAA region and being separated from the second GAA region by a second dielectric material.

### Claim 20 (depends on 16)

The method of claim 16, further comprising:
providing additional FM conductors to create a plurality of FM conductors extending in the X direction and spaced apart from each other along a Y direction; and
providing additional BM conductors to create a plurality of BM conductors extending in the X direction and spaced apart from each other along the Y direction.

### Claim 21 (depends on 20)

The method of claim 20, wherein the plurality of FM conductors extending in the X direction consists of four or fewer FM conductors extending in the X direction.

### Claim 22 (depends on 20)

The method of claim 20, wherein the plurality of BM conductors extending in the X direction consists of four or fewer BM conductors extending in the X direction.

### Claim 23 (depends on 20)

The method of claim 20, wherein the plurality of FM conductors extending in the X direction consists of three or fewer FM conductors extending in the X direction.

### Claim 24 (depends on 20)

The method of claim 20, wherein the plurality of BM conductors extending in the X direction consists of three or fewer BM conductors extending in the X direction.

### Claim 25 (depends on 20)

The method of claim 20, further comprising providing a second vertical connector that electrically couples the second S/D region to the fourth S/D region by direct contact with both the second S/D region and the fourth S/D region.

### Claim 26 (depends on 25)

The method of claim 25, further comprising electrically coupling the second vertical connector to another of the plurality of FM conductors, another of the plurality of BM conductors, or both.

### Claim 27

A method of fabricating a semiconductor structure, the method comprising:
providing a frontside (FS) metal (FM) layer comprising a plurality of FM conductors extending in an X direction and separated from each other along a Y direction;
providing a vertical connector extending in a Z direction and being electrically coupled to one of the plurality of FM conductors; and
providing a backside (BS) metal (BM) layer disposed below the FM layer in the Z direction and comprising a plurality of BM conductors extending in the X direction and separated from each other along the Y direction, one of the plurality of BM conductors being electrically coupled to the vertical connector.