# US 2025/0098211 A1 · Method for manufacturing semiconductor device and semiconductor device

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- Number: US 2025/0098211 A1
- Document ID: US20250098211A1
- Status: Published application
- Kind: A1
- Application number: 18/969,589
- Filed: 2024-12-05
- Published: 2025-03-20
- Earliest claimed: 2020-09-14
- Assignees: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation
- Applicants: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation
- Inventors: Kohei OASA; Kouta TOMITA
- Web page: https://patentgrep.com/patent/US20250098211A1

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/2527: {for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies}
- H10P 30/202: {characterised by the semiconductor materials}
- H10P 30/21: {of electrically active species}
- H10P 30/212: {Through-implantation}
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10P 50/642: {Chemical etching}
- H10W 20/076: {in via holes or trenches}
- H10D 30/0295: {using recessing of the source electrodes}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10P 30/204: {into Group IV semiconductors}
- H10P 32/1406: {by ion implantation}
- H10P 32/171: {being group IV material}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for manufacturing a semiconductor device includes forming a trench in a first semiconductor layer of a first conductivity type; filling a first insulating film into the trench; etching the first insulating film to cause an upper surface of the first insulating film to recede lower than an opening of the trench and to expose a sidewall of an upper portion of the trench from under the first insulating film; forming a second-conductivity-type semiconductor region in a region of the first semiconductor layer next to the upper portion of the trench by implanting a second-conductivity-type impurity through the sidewall of the upper portion of the trench into the first semiconductor layer and by diffusing the second-conductivity-type impurity; and forming a gate electrode on the first insulating film in the upper portion of the trench after the forming of the second-conductivity-type semiconductor region.

## Claims

### Claim at position 1

1-7. (canceled)

### Claim 8

A semiconductor device, comprising:
a semiconductor part including a first semiconductor layer of a first conductivity type;
a first insulating film formed in the semiconductor part;
a gate electrode located on the first insulating film;
a second-conductivity-type semiconductor region located on the first semiconductor layer in a region of the semiconductor part next to the gate electrode;
a second insulating film located between the gate electrode and the second-conductivity-type semiconductor region; and
a first-conductivity-type semiconductor region located on the second-conductivity-type semiconductor region,
the second-conductivity-type semiconductor region including a first portion and a second portion,
the first portion being positioned between the second insulating film and the second portion and contacting the second insulating film,
a second-conductivity-type impurity concentration of the first portion being greater than a second-conductivity-type impurity concentration of the second portion.

### Claim 9 (depends on 8)

The device according to claim 8, wherein
a boundary between the first portion and the second insulating film protrudes lower than the second portion.

### Claim 10 (depends on 8)

The device according to claim 8, wherein
a lower end of the second-conductivity-type semiconductor region is positioned lower than a lower end of the gate electrode.

### Claim 11 (depends on 8)

The device according to claim 8, wherein
a lowermost end of the second-conductivity-type semiconductor region is positioned at a boundary between the first portion and the second insulating film.

### Claim 12 (depends on 8)

The device according to claim 8, further comprising:
a first electrode electrically connected with the first semiconductor layer; and
a second electrode electrically connected with the first-conductivity-type semiconductor region and the second-conductivity-type semiconductor region.

### Claim 13 (depends on 12)

The device according to claim 12, further comprising:
a field plate electrode located in the first insulating film,
the field plate electrode being electrically connected with the second electrode.

### Claim 14 (depends on 8)

The device according to claim 8, wherein
the gate electrode, the first-conductivity-type semiconductor region, and the second-conductivity-type semiconductor region are formed in stripe shapes.

### Claim 15 (depends on 8)

The device according to claim 8, wherein
the gate electrode is located in a hole formed in the semiconductor part, and
the hole includes three or more sidewalls.