# US 2025/0098200 A1 · Gallium nitride enhancement mode device

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- Number: US 2025/0098200 A1
- Document ID: US20250098200A1
- Status: Published application
- Kind: A1
- Application number: 18/940,279
- Filed: 2024-11-07
- Published: 2025-03-20
- Earliest claimed: 2018-09-11
- Assignees: Analog Devices, Inc.
- Applicants: Analog Devices, Inc.
- Inventors: James G. Fiorenza; Puneet Srivastava; Daniel Piedra
- Web page: https://patentgrep.com/patent/US20250098200A1

## CPC

- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 1/43: Resistors having PN junctions
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 62/124: {Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions}
- H10D 62/343: {Gate regions of field-effect devices having PN junction gates}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 62/378: {Contact regions to the substrate regions}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 84/01: Manufacture or treatment
- H10D 84/05: using Group III-V technology
- H10D 84/84: Combinations of enhancement-mode IGFETs and depletion-mode IGFETs
- H10P 30/206: {into Group III-V semiconductors}
- H10P 30/212: {Through-implantation}
- H10P 30/28: characterised by an annealing step, e.g. for activation of dopants
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10P 30/22: using masks
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An enhancement mode compound semiconductor field-effect transistor (FET) includes a source, a drain, and a gate located therebetween. The transistor further includes a first gallium nitride-based hetero-interface located under the gate and a buried region, located under the first hetero-interface, the buried p-type region configured to determine an enhancement mode FET turn-on threshold voltage to permit current flow between the source and the drain.

## Claims

### Claim 1

(canceled)

### Claim 2

A method of manufacturing a semiconductor device, the method comprising:
forming a layer of deactivated p-type material over a substrate;
forming a layer of a first compound semiconductor material over the layer of deactivated p-type material;
forming a channel layer having a hetero-structure by forming a layer of a second compound semiconductor material over the layer of the first compound semiconductor material;
forming a recess in the channel layer and the layer of deactivated p-type material; and
forming an activated p-type region adjacent the recess in the layer of deactivated p-type material by annealing the semiconductor device while leaving a deactivated p-type region.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
forming a gate electrode;
forming a source electrode within the recess and adjacent the gate electrode; and
forming a drain electrode.

### Claim 4 (depends on 3)

The method of claim 3, wherein the recess is a first recess, the method comprising:
forming a second recess within the channel layer, and wherein forming the gate electrode includes:
forming the gate electrode at least partially within the second recess.

### Claim 5 (depends on 3)

The method of claim 3, wherein forming the activated p-type region in the layer of deactivated p-type material includes:
forming the activated p-type region under the gate electrode.

### Claim 6 (depends on 3)

The method of claim 3, wherein forming the source electrode includes:
forming the source electrode laterally within 100 nanometers of the gate electrode.

### Claim 7 (depends on 2)

The method of claim 2, wherein annealing the semiconductor device includes:
annealing in an environment comprising nitrogen.

### Claim 8 (depends on 2)

The method of claim 2, wherein annealing the semiconductor device includes:
annealing in an environment comprising ammonia.

### Claim 9 (depends on 2)

The method of claim 2, wherein annealing the semiconductor device includes:
annealing at a temperature between 1100 and 1200 degrees Celsius.

### Claim 10 (depends on 2)

The method of claim 2, wherein the first compound semiconductor material comprises gallium nitride (GaN) and the second compound semiconductor material comprises aluminum gallium nitride (AlGaN).

### Claim 11 (depends on 2)

The method of claim 2, wherein forming the layer of deactivated p-type material includes forming a layer of deactivated p-type gallium nitride (p-GaN).

### Claim 12 (depends on 2)

The method of claim 2, wherein the semiconductor device is an enhancement mode semiconductor device.

### Claim 13

A semiconductor device comprising:
a substrate;
a layer of deactivated p-type material disposed over the substrate;
a layer of a first compound semiconductor material disposed over the layer of deactivated p-type material;
a channel layer having a hetero-structure comprising a layer of a second compound semiconductor material disposed over the layer of the first compound semiconductor material;
a recess formed in the channel layer and the layer of deactivated p-type material;
an activated p-type region formed in the layer of deactivated p-type material and adjacent the recess;
a deactivated p-type region formed adjacent to the activated p-type region;
a source electrode formed in the recess; and
a gate electrode formed over the activated p-type region and adjacent the source electrode.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the recess is a first recess, the semiconductor device further comprising:
a second recess formed within the channel layer, wherein the gate electrode is formed at least partially within the second recess.

### Claim 15 (depends on 13)

The semiconductor device of claim 13, wherein the source electrode is formed laterally within 100 nanometers of the gate electrode.

### Claim 16 (depends on 13)

The semiconductor device of claim 13, wherein the semiconductor device is an enhancement mode semiconductor device.

### Claim 17 (depends on 13)

The semiconductor device of claim 13, wherein the first compound semiconductor material comprises gallium nitride (GaN) and the second compound semiconductor material comprises aluminum gallium nitride (AlGaN).

### Claim 18 (depends on 13)

The semiconductor device of claim 13, wherein the layer of deactivated p-type material includes deactivated p-type gallium nitride (p-GaN).

### Claim 19

A semiconductor device comprising:
a substrate;
a layer of deactivated p-type material disposed over the substrate;
a layer of a first compound semiconductor material disposed over the layer of deactivated p-type material;
a channel layer having a hetero-structure comprising a layer of a second compound semiconductor material disposed over the layer of the first compound semiconductor material;
a first recess formed in the channel layer and the layer of deactivated p-type material;
a second recess formed in the channel layer;
an activated p-type region formed in the layer of deactivated p-type material and adjacent the first recess;
a deactivated p-type region formed adjacent to the activated p-type region;
a source electrode formed in the first recess; and
a gate electrode formed over the activated p-type region and adjacent the source electrode, wherein the gate electrode is formed within the second recess.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein the source electrode is formed laterally within 100 nanometers of the gate electrode.

### Claim 21 (depends on 19)

The semiconductor device of claim 19, wherein the layer of deactivated p-type material includes deactivated p-type gallium nitride (p-GaN).