# US 2025/0098197 A1 · Dielectric Fin Structures for Semiconductor Devices

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- Number: US 2025/0098197 A1
- Document ID: US20250098197A1
- Status: Published application
- Kind: A1
- Application number: 18/444,211
- Filed: 2024-02-16
- Published: 2025-03-20
- Earliest claimed: 2023-09-15
- Assignees: Taiwan Semiconductor Manufacturing Co., Lid.
- Applicants: Taiwan Semiconductor Manufacturing Company, Lid.
- Inventors: Tzu-Ging LIN
- Web page: https://patentgrep.com/patent/US20250098197A1

## CPC

- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present disclosure describes a semiconductor device having a dielectric fin structure. The semiconductor device includes a channel structure on a substrate and a dielectric fin structure on the substrate and adjacent to the channel structure. The channel structure extends along a first direction. The dielectric fin structure includes a stiff dielectric material and extends along a second direction parallel to the first direction. The semiconductor device further includes an isolation structure extending through the channel structure. The isolation structure is in contact with the dielectric fin structure.

## Claims

### Claim 1

A semiconductor structure, comprising:
a channel structure on a substrate, wherein the channel structure extends along a first direction;
a dielectric fin structure on the substrate and adjacent to the channel structure, wherein the dielectric fin structure comprises a stiff dielectric material and extends along a second direction parallel to the first direction; and
an isolation structure extending through the channel structure, wherein the isolation structure is in contact with the dielectric fin structure.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the dielectric fin structure is on a top surface of an isolation layer and the stiff dielectric material has a Young's modulus greater than about 75 GPa.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, further comprising a gate structure wrapped around the channel structure, wherein the gate structure is between the channel structure and the dielectric fin structure.

### Claim 4 (depends on 3)

The semiconductor structure of claim 3, wherein a top surface of the dielectric fin structure is below a top surface of the gate structure.

### Claim 5 (depends on 3)

The semiconductor structure of claim 3, wherein a ratio of a height of the isolation structure to a height of the gate structure ranges from about 0.15 to about 0.3.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein a top surface of the dielectric fin structure is below a top surface of the isolation structure.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein a bottom surface of the dielectric fin structure is at a same level or above a top surface of the channel structure.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, wherein the isolation structure extends into the substrate and the dielectric fin structure is surrounded by the isolation structure.

### Claim 9 (depends on 1)

The semiconductor structure of claim 1, wherein the isolation structure comprises a liner in contact with the dielectric fin structure and a dielectric fill on the liner.

### Claim 10

A semiconductor device, comprising:
a plurality of channel structures on a substrate;
a plurality of dielectric fin structures comprising a stiff dielectric material on the substrate, wherein the plurality of channel structures and the plurality of dielectric fin structures are arranged in an alternate configuration;
a gate structure surrounding the plurality of channel structures and the plurality of dielectric fin structures; and
an isolation structure extending through the gate structure and at least one of the plurality of channel structures, wherein the isolation structure is in contact with the at least one of the plurality of dielectric fin structures.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the plurality of dielectric fin structures are on a top surface of an isolation layer and the stiff dielectric material has a Young's modulus greater than about 75 GPa.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein top surfaces of the plurality of dielectric fin structures are below a top surface of the gate structure.

### Claim 13 (depends on 10)

The semiconductor device of claim 10, wherein top surfaces of the gate structure and the isolation structure are coplanar.

### Claim 14 (depends on 10)

The semiconductor device of claim 10, wherein bottom surfaces of the plurality of dielectric fin structures are at a same level as or above top surfaces of the plurality of channel structures.

### Claim 15 (depends on 10)

The semiconductor device of claim 10, wherein the isolation structure extends through the plurality of channel structures into the substrate.

### Claim 16

A method, comprising:
forming a channel structure on a substrate, wherein the channel structure extends along a first direction;
forming a dielectric fin structure on the substrate and adjacent to the channel structure, wherein the dielectric fin structure comprises a stiff dielectric material and extends along a second direction parallel to the first direction; and
forming an isolation structure extending through the channel structure, wherein the isolation structure is in contact with the dielectric fin structure.

### Claim 17 (depends on 16)

The method of claim 16, further comprising forming a gate structure wrapped around the channel structure, wherein the gate structure is between the channel structure and the dielectric fin structure.

### Claim 18 (depends on 16)

The method of claim 16, wherein forming the dielectric fin structure comprises:
forming an isolation layer on the channel structure and an adjacent channel structure;
etching the isolation layer to form an opening between the channel structure and the adjacent channel structure, wherein a bottom surface of the opening is at a same level as or above a top surface of the channel structure; and
filling the opening with the stiff dielectric material, wherein the stiff dielectric material has a Young's modulus greater than about 75 GPa.

### Claim 19 (depends on 16)

The method of claim 16, wherein forming the isolation structure comprises:
forming a sacrificial gate structure on the channel structure and the dielectric fin structure;
etching through the sacrificial gate structure and the channel structure to form an opening;
depositing a dielectric material in the opening, wherein the dielectric material is in contact with the dielectric fin structure; and
replacing the sacrificial gate structure with a metal gate structure.

### Claim 20 (depends on 16)

The method of claim 16, wherein forming the isolation structure comprises:
forming a metal gate structure on the channel structure and the dielectric fin structure;
etching through the metal gate structure and the channel structure to form an opening; and
depositing a dielectric material in the opening, wherein the dielectric material is in contact with the dielectric fin structure.