# US 2025/0098191 A1 · Manufacturing method of semiconductor device and semiconductor device

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- Number: US 2025/0098191 A1
- Document ID: US20250098191A1
- Status: Published application
- Kind: A1
- Application number: 18/598,456
- Filed: 2024-03-07
- Published: 2025-03-20
- Earliest claimed: 2023-09-15
- Assignees: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation
- Applicants: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation
- Inventors: Kazusa ARIMA
- Web page: https://patentgrep.com/patent/US20250098191A1

## CPC

- H10D 12/441: {Vertical IGBTs}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 12/032: {of vertical IGBTs}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 54/90: Auxiliary processes or arrangements
- H10D 12/415: {having edge termination structures}
- H10D 30/665: {having edge termination structures}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A manufacturing method a semiconductor device according to an embodiment is a manufacturing method a semiconductor device located on a semiconductor wafer within a region surrounded by a first dicing line extending in a first direction and a second dicing line perpendicular to the first direction, the semiconductor device including a cell region and a termination region, the cell region including a semiconductor device located within a semiconductor substrate, the termination region including a metal wiring line located on the semiconductor substrate and electrically connected to the semiconductor device. In this method, a stopper film is formed around the metal wiring line in the termination region, a protection film covering the metal wiring line and ending at a side surface of the stopper film is formed, and the semiconductor wafer is diced along the first dicing line and the second dicing line.

## Claims

### Claim 1

A manufacturing method of a semiconductor device, the semiconductor device being located on a semiconductor wafer within a region surrounded by a first dicing line extending in a first direction and a second dicing line perpendicular to the first direction, the semiconductor device including a cell region and a termination region, the cell region including a semiconductor device located within a semiconductor substrate, the termination region including a metal wiring line located on the semiconductor substrate and electrically connected to the semiconductor device, the method comprising:
forming a stopper film around the metal wiring line in the termination region;
forming a protection film, the protection film covering the metal wiring line and ending at a side surface of the stopper film; and
dicing the semiconductor wafer along the first dicing line and the second dicing line.

### Claim 2 (depends on 1)

The manufacturing method according to claim 1, wherein the stopper film includes an oxide film, a nitride film, or an electrically conductive film.

### Claim 3 (depends on 1)

The manufacturing method according to claim 1, wherein a height of the stopper film is greater than a thickness of the metal wiring line.

### Claim 4 (depends on 2)

The manufacturing method according to claim 2, further comprising:
covering the metal wiring line and an upper surface of the semiconductor substrate with the oxide film, the nitride film, or the electrically conductive film;
applying a photoresist to, within the oxide film, the nitride film, or the electrically conductive film, a portion that is to be left as the stopper film;
etching the oxide film, the nitride film, or the electrically conductive film using the photoresist as a mask; and
removing the photoresist.

### Claim 5 (depends on 1)

The manufacturing method according to claim 1, wherein the stopper film extends in an intersection region between the first dicing line and the second dicing line.

### Claim 6 (depends on 1)

The manufacturing method according to claim 1, wherein the stopper film ends at the termination region and does not extend in an intersection region R between the first dicing line and the second dicing line.

### Claim 7 (depends on 1)

The manufacturing method according to claim 1, wherein the protection film includes a polyimide film.

### Claim 8 (depends on 1)

The manufacturing method according to claim 1, wherein the semiconductor device includes an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

### Claim 9

A semiconductor device comprising:
a cell region including a semiconductor device; and
a termination region surrounding the cell region,
wherein the termination region includes:
a metal wiring line electrically connected to the semiconductor device;
a protection film covering the metal wiring line; and
a stopper film having a side surface being in contact with an end portion of the protection film.

### Claim 10 (depends on 9)

The semiconductor device according to claim 9, wherein the stopper film includes an oxide film, a nitride film, or an electrically conductive film.

### Claim 11 (depends on 9)

The semiconductor device according to claim 9, wherein a height of the stopper film is greater than a thickness of the metal wiring line.

### Claim 12 (depends on 9)

The semiconductor device according to claim 9, wherein the protection film includes a polyimide film.

### Claim 13 (depends on 9)

The semiconductor device according to claim 9, wherein the semiconductor device includes an IGBT or a MOSFET.