# US 2025/0098189 A1 · Bipolar transistor and method of making a bipolar transistor

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- Number: US 2025/0098189 A1
- Document ID: US20250098189A1
- Status: Published application
- Kind: A1
- Application number: 18/824,976
- Filed: 2024-09-05
- Published: 2025-03-20
- Earliest claimed: 2023-09-18
- Assignees: NXP B.V.
- Applicants: NXP B.V.
- Inventors: Jay Paul John; James Albert Kirchgessner; Johannes Josephus Theodorus Marinus Donkers; Ljubo Radic; Patrick Sebel
- Web page: https://patentgrep.com/patent/US20250098189A1

## CPC

- H10D 10/021: {of heterojunction BJTs [HBT]}
- H10D 10/821: {Vertical heterojunction BJTs}
- H10D 62/136: {of heterojunction BJTs (vertical heterojunction BJTs having one or more non-monocrystalline Group IV elements H10D10/861)}
- H10D 62/138: {Pedestal collectors}
- H10D 62/177: {Base regions of bipolar transistors, e.g. BJTs or IGBTs}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A bipolar transistor and a method of making a bipolar transistor. The method includes providing a semiconductor substrate having a major surface, one or more layers located beneath the major surface for forming an intrinsic base, and a collector. The method also includes depositing a first oxide layer on the major surface, depositing a second oxide layer on the first oxide layer, and depositing an extrinsic base layer on the second oxide layer. The method further includes forming an emitter window through the extrinsic base layer. The method also includes removing at least a part of the second oxide layer to form a first cavity and forming an initial part of a base link region in the first cavity. The method also includes removing at least a part of the first oxide layer to form a second cavity and filling the second cavity to form a completed base link region.

## Claims

### Claim at position 1

1-15. (canceled)

### Claim 16

A method of making a bipolar transistor, the method comprising:
providing a semiconductor substrate that includes a major surface, one or more layers located beneath the major surface for forming an intrinsic base of the bipolar transistor, and a collector located beneath the one or more layers;
depositing a first oxide layer on the major surface;
depositing a second oxide layer on the first oxide layer;
depositing an extrinsic base layer on the second oxide layer;
forming an emitter window through the extrinsic base layer;
removing at least a part of the second oxide layer to form a first cavity between the first oxide layer and the extrinsic base layer;
forming an initial part of a base link region in the first cavity;
removing at least a part of the first oxide layer to form a second cavity between the major surface and the initial part of the base link region;
filling the second cavity to form a completed base link region from the initial part of the base link region and the filled cavity; and
forming an emitter in the emitter window.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
prior to depositing the extrinsic base layer, patterning the first and second oxide layers to form an island comprising a remaining part of the of the first oxide layer and a remaining part of the second oxide layer.

### Claim 18 (depends on 17)

The method of claim 17, wherein depositing the extrinsic base layer comprises:
depositing the extrinsic base layer on the island and on parts of the major surface that surround a periphery of the island.

### Claim 19 (depends on 17)

The method of claim 17, wherein forming the emitter window exposes a central region of the island.

### Claim 20 (depends on 17)

The method of claim 17, wherein:
removing at least a part of the second oxide layer includes removing the remaining part of the second oxide layer; and
removing at least a part of the first oxide layer includes removing the remaining part of the first oxide layer.

### Claim 21 (depends on 16)

The method of claim 16, wherein parts of the first oxide layer and the second oxide layer located between the extrinsic base layer and the major surface, which are not removed during formation of the first cavity and formation of the second cavity, are configured to reduce a collector-base junction capacitance of the bipolar transistor.

### Claim 22 (depends on 16)

The method of claim 16, wherein the second oxide layer has a faster etch rate than the first oxide layer, to allow preferential removal of the second oxide layer relative to the first oxide layer during formation of the first cavity.

### Claim 23 (depends on 16)

The method of claim 16, further comprising:
prior to depositing the extrinsic base layer, patterning the first and second oxide layers to form an island that includes a remaining part of the of the first oxide layer and a remaining part of the second oxide layer; and
wherein
the second oxide layer has a faster etch rate than the first oxide layer, to allow preferential removal of the second oxide layer relative to the first oxide layer during formation of the first cavity, and
the faster etch rate of the second oxide layer causes the remaining part of the second oxide layer to have a smaller footprint than the remaining part of the first oxide layer.

### Claim 24 (depends on 16)

The method of claim 16, wherein forming the initial part of a base link region in the first cavity comprises a silicon (Si) and/or silicon germanium (SiGe) growth step.

### Claim 25 (depends on 16)

The method of claim 16, further comprising:
forming an emitter spacer in the emitter window after forming the completed base link region and prior to forming the emitter in the emitter window.

### Claim 26 (depends on 16)

The method of claim 16, wherein filling the second cavity comprises:
using a hydrogen sealing process to fill the second cavity.

### Claim 27 (depends on 16)

The method of claim 16, wherein filling the second cavity comprises:
using a selective epitaxial growth step to fill the second cavity.

### Claim 28 (depends on 16)

The method of claim 16, wherein the first oxide layer is configured to protect the major surface during formation of the initial part of a base link region.

### Claim 29 (depends on 16)

The method of claim 16, wherein the first oxide layer is thinner than the second oxide layer.

### Claim 30

A bipolar transistor manufactured by a method comprising:
providing a semiconductor substrate that includes a major surface, one or more layers located beneath the major surface for forming an intrinsic base of the bipolar transistor, and a collector located beneath the one or more layers;
depositing a first oxide layer on the major surface;
depositing a second oxide layer on the first oxide layer;
depositing an extrinsic base layer on the second oxide layer;
forming an emitter window through the extrinsic base layer;
removing at least a part of the second oxide layer to form a first cavity between the first oxide layer and the extrinsic base layer;
forming an initial part of a base link region in the first cavity;
removing at least a part of the first oxide layer to form a second cavity between the major surface and the initial part of the base link region;
filling the second cavity to form a completed base link region from the initial part of the base link region and the filled cavity; and
forming an emitter in the emitter window.

### Claim 31 (depends on 30)

The bipolar transistor of claim 30, wherein the method further comprises:
prior to depositing the extrinsic base layer, patterning the first and second oxide layers to form an island comprising a remaining part of the of the first oxide layer and a remaining part of the second oxide layer.

### Claim 32 (depends on 31)

The bipolar transistor of claim 31, wherein depositing the extrinsic base layer comprises:
depositing the extrinsic base layer on the island and parts of the major surface that surround a periphery of the island.

### Claim 33 (depends on 31)

The bipolar transistor of claim 31, wherein forming the emitter window exposes a central region of the island.

### Claim 34 (depends on 31)

The bipolar transistor of claim 31, wherein:
removing at least a part of the second oxide layer includes removing the remaining part of the second oxide layer; and
removing at least a part of the first oxide layer includes removing the remaining part of the first oxide layer.

### Claim 35 (depends on 30)

The bipolar transistor of claim 30, wherein parts of the first oxide layer and the second oxide layer located between the extrinsic base layer and the major surface, which are not removed during formation of the first cavity and formation of the second cavity, are configured to reduce a collector-base junction capacitance of the bipolar transistor.