# US 2025/0098166 A1 · Semiconductor memory device with a three-dimensional stacked memory cell structure

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- Number: US 2025/0098166 A1
- Document ID: US20250098166A1
- Status: Published application
- Kind: A1
- Application number: 18/964,178
- Filed: 2024-11-29
- Published: 2025-03-20
- Earliest claimed: 2011-06-28
- Assignees: Kioxia Corporation
- Applicants: Kioxia Corporation
- Inventors: Tomoo HISHIDA; Yoshihisa IWATA
- Web page: https://patentgrep.com/patent/US20250098166A1

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 7/18: Bit line organisation; Bit line lay-out
- G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- H10B 43/30: characterised by the memory core region
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- H10W 20/43: Layouts of interconnections
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 2213/71: Three dimensional array
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.

## Claims

### Claim 1

A semiconductor memory device, comprising:
a semiconductor substrate extending in a first direction, a second direction, and a third direction, the first, second, and third directions crossing one another;
a plurality of word lines laminated in the third direction above the semiconductor substrate in the third direction, and each extending in the first direction and the second direction,
a plurality of memory pillars each penetrating the word lines in the third direction;
a plurality of bit lines, arranged in the second direction, and each extending in the first direction; and
a plurality of contacts connecting the bit lines and the memory pillars, respectively,
wherein
the memory pillars include
a first memory pillar,
a second memory pillar overlapping the first memory pillar when viewed in the first direction,
a third memory pillar overlapping the first memory pillar when viewed in the second direction, and
a fourth memory pillar overlapping the third memory pillar when viewed in the first direction and overlapping the fourth memory pillar when viewed in the second direction,
the bit lines a first bit line overlapping the first memory pillar and the second memory pillar when viewed in the third direction,
a second bit line located on one side of the first bit line in the second direction and overlapping the first memory pillar and the second memory pillar when viewed in the third direction,
a third bit line located on one side of the second bit line in the second direction and overlapping the third memory pillar and the fourth memory pillar when viewed in the third direction, and
a fourth bit line located on one side of the third bit line in the second direction and overlapping the third memory pillar and the fourth memory pillar when viewed in the third direction, and
the contacts include
a first contact connecting the first memory pillar and the first bit line,
a second contact connecting the second memory pillar and the second bit line,
a third contact connecting the third memory pillar and the third bit line, and
a fourth contact connecting the fourth memory pillar and the fourth bit line.

### Claim 2 (depends on 1)

The semiconductor memory device according to claim 1, wherein
the first memory pillar is not electrically connected to the second bit line,
the second memory pillar is not electrically connected to the first bit line,
the third memory pillar is not electrically connected to the fourth bit line, and
the fourth memory pillar is not electrically connected to the third bit line.

### Claim 3 (depends on 1)

The semiconductor memory device according to claim 1, wherein
the bit lines are provided above the word lines in the third direction.

### Claim 4 (depends on 1)

The semiconductor memory device according to claim 1, further comprising:
a source line provided above the word lines in the third direction and extending in the first direction and the second direction.

### Claim 5 (depends on 1)

The semiconductor memory device according to claim 1, further comprising:
a circuitry formed on the semiconductor substrate.

### Claim 6 (depends on 5)

The semiconductor memory device according to claim 5, wherein
the circuitry includes
a first sense amplifier connected to the first bit line,
a second sense amplifier connected to the second bit line,
a third sense amplifier connected to the third bit line, and
a fourth sense amplifier connected to the fourth bit line.

### Claim 7 (depends on 6)

The semiconductor memory device according to claim 6, wherein
the bit lines further includes
a fifth bit line located between the first bit line and the second bit line in the second direction, and
a sixth bit line located between the third bit line and the fourth bit line in the second direction.

### Claim 8 (depends on 7)

The semiconductor memory device according to claim 7, wherein
the memory pillars further include
a fifth memory pillar, and
a sixth memory pillar overlapping the fifth memory pillar when viewed in the second direction, and
the contacts further include
a fifth contact connecting the fifth memory pillar and the fifth bit line, and
a sixth contact connecting the sixth memory pillar and the sixth bit line.

### Claim 9 (depends on 8)

The semiconductor memory device according to claim 8, wherein
the first sense amplifier is connected to the first bit line and the fifth bit line, and
the third sense amplifier is connected to the third bit line and the sixth bit line.

### Claim 10 (depends on 6)

The semiconductor memory device according to claim 6, wherein
the bit lines further include
a seventh bit line located on one side of the second bit line in the second direction, and
an eighth bit line located on one side of the fourth bit line in the second direction.

### Claim 11 (depends on 10)

The semiconductor memory device according to claim 10, wherein
the memory pillars further include
a seventh memory pillar, and
an eighth memory pillar overlapping the seventh memory pillar when viewed in the second direction, and
the contacts further include
a seventh contact connecting the seventh memory pillar and the seventh bit line, and
an eighth contact connecting the eighth memory pillar and the eighth bit line.

### Claim 12 (depends on 11)

The semiconductor memory device according to claim 11, wherein
the second sense amplifier is connected to the second bit line and the seventh bit line, and
the fourth sense amplifier is connected to the fourth bit line and the eighth bit line.

### Claim 13 (depends on 11)

The semiconductor memory device according to claim 11, wherein
the seventh memory pillar is located between the first memory pillar and the third memory pillar in the second direction when viewed in the first direction, and
the eighth memory pillar is located on one side of the third memory pillar in the second direction when viewed in the first direction.

### Claim 14 (depends on 13)

The semiconductor memory device according to claim 13, wherein
each of the seventh memory pillar and the eighth memory pillar is located between the first memory pillar and the second memory pillar in the first direction when viewed in the second direction.