Memory devices including pad structures
AssigneeMicron Technology, Inc.
InventorsErwin E. Yu, Michele Piccardi, Surendranath C. Eruvuru
Life of this patent
Estimating the term…
Abstract
A microelectronic device comprises a base structure, a memory array overlying the base structure, and a conductive pad tier overlying the memory array. The base structure comprises a logic region including logic devices. The memory array comprises vertically extending strings of memory cells within a horizontal area of the logic region of the base structure. The conductive pad tier comprises first conductive pads substantially outside of the horizontal area of the logic region of the base structure, and second conductive pads horizontally neighboring the first conductive pads and within the horizontal area of the logic region of the base structure. Memory devices and electronic systems are also described.
Claims20
A 3D NAND Flash memory device, comprising:
- a base structure having a logic region including logic circuitry therein;
- a stack structure comprising tiers vertically stacked relative to one another and respectively including conductive material and insulative material vertically neighboring the conductive material, the stack structure having an array region including vertically extending strings of memory cells therein;
- and
- multiple rows of pad structures vertically overlying the stack structure and horizontally extending in parallel with one another is a first direction, the multiple rows of pad structures comprising:
- a first row of pad structures horizontally overlapping each of the logic region of the base structure and the array region of the stack structure in a second direction orthogonal to the first direction;
- and
- a second row of pad structures horizontally offset from each of the logic region of the base structure and the array region of the stack structure in the second direction.
A non-volatile memory device, comprising:
- a base structure comprising:
- a first horizontal area including at least one logic device;
- and
- a second horizontal area horizontally offset from the first horizontal area and substantially free of any logic devices;
- and
- an additional structure vertically offset for the base structure and comprising:
- a third horizontal area including:
- a stack structure comprising levels of conductive material vertically interleaved with levels of insulative material;
- and
- non-volatile memory cells within a vertical span of the stack structure;
- a fourth horizontal area horizontally offset from the third horizontal area and comprising conductive contacts respectively vertically extending across substantially an entirety of the vertical span of the stack structure;
- and
- conductive pads vertically overlying and coupled to the conductive contacts, the conductive pads comprising:
- first conductive pads respectively substantially confined within the first horizontal area of the base structure;
- and
- second conductive pads respectively substantially confined within the second horizontal area of the base structure.
A memory device, comprising:
- a base structure comprising a region including logic circuitry;
- a stack structure vertically overlying the base structure and comprising conductive material vertically alternating with insulative material;
- cell pillar structures respectively comprising semiconductor material vertically extending through the stack structure;
- and
- conductive pads vertically overlying the stack structure within overlapping horizontal areas of the stack structure and the region of the base structure;
- and
- additional conductive pads substantially vertically aligned with the conductive pads and outside of the overlapping horizontal areas of the stack structure and the region of the base structure.
Dependencies are inferred from the claim text.