# US 2025/0098149 A1 · Ultra-thin body array transistor for 4f2

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2025/0098149 A1
- Document ID: US20250098149A1
- Status: Published application
- Kind: A1
- Application number: 18/884,775
- Filed: 2024-09-13
- Published: 2025-03-20
- Earliest claimed: 2023-09-20
- Assignees: Applied Materials, Inc.
- Applicants: Applied Materials, Inc.
- Inventors: Tong LIU; Sony VARGHESE
- Web page: https://patentgrep.com/patent/US20250098149A1

## CPC

- H10B 12/395: {the transistor being vertical}
- H10B 12/0383: {wherein the transistor is vertical}
- H10B 12/05: {Making the transistor}
- H10B 12/482: {Bit lines}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present technology includes vertical cell array transistor (VCAT) that include a bit line arranged in a first horizontal direction and a word line arranged in a second horizontal direction. The arrays include a channel extending in a vertical direction generally orthogonal to the first direction and the second horizontal direction, such that the bit line intersects with a source/drain region of the plurality of channels, and the word lines intersect with gate regions of the plurality of channels. Arrays include where the channels have at least one source/drain region and a channel body disposed between the first end and the second end. Arrays include where the channel body has a thickness that is greater than or about 5% less than a thickness of at least a portion of the at least one source/drain region.

## Claims

### Claim 1

A vertical cell array transistor (VCAT), comprising:
one or more bit lines arranged in a first horizontal direction;
one or more word lines arranged in a second horizontal direction;
one or more channels extending in a vertical direction that is generally orthogonal to the first horizontal direction and the second horizontal direction such that the one or more word lines intersect with a gate region of the one or more channels;
wherein the one or more channels have at least one source/drain region at a first end, a second end, or both a first end and a second end of the one or more channels and a channel body disposed between the first end and the second end, wherein the channel body has a thickness that is greater than or about 5% less than a thickness of at least a portion of the at least one source/drain region.

### Claim 2 (depends on 1)

The vertical cell array transistor (VCAT) of claim 1, wherein the one or more channels comprise a first source/drain region at a first end and a second source/drain region at the second end, wherein the channel body has a thickness that is greater than or about 5% less than a thickness of at least a portion of the first source/drain region and the second source/drain region.

### Claim 3 (depends on 1)

The vertical cell array transistor (VCAT) of claim 1, wherein at least a portion of the at least one source/drain region has a greater thickness than a second portion of the at least one source/drain region.

### Claim 4 (depends on 1)

The vertical cell array transistor (VCAT) of claim 1, wherein greater than or about 20% of the at least one source/drain region has a thickness greater than the thickness of the channel body.

### Claim 5 (depends on 4)

The vertical cell array transistor (VCAT) of claim 4, wherein the at least one source/drain region has a contact end and an internal end, wherein the contact end has the thickness greater than the thickness of the channel body.

### Claim 6 (depends on 5)

The vertical cell array transistor (VCAT) of claim 5, wherein the internal end has a thickness generally equal to a thickness of the channel body.

### Claim 7 (depends on 2)

The vertical cell array transistor (VCAT) of claim 2, wherein the channel body has a thickness that is greater than or about 10% less than a thickness of at least a portion of the first source/drain region and the second source/drain region.

### Claim 8 (depends on 1)

The vertical cell array transistor (VCAT) of claim 1, wherein the channel body has a thickness of less than 11 nm.

### Claim 9 (depends on 8)

The vertical cell array transistor (VCAT) of claim 8, wherein the channel body has a thickness of less than or about 10 nm.

### Claim 10

A vertical cell array transistor (VCAT), comprising:
a plurality of bit lines arranged in a first horizontal direction;
a plurality of word lines arranged in a second horizontal direction;
a plurality of channels extending in a vertical direction that is generally orthogonal to the first horizontal direction and the second horizontal direction such that the plurality of word lines intersect with a gate region of the plurality of channels;
wherein the plurality of channels each have a first source/drain region at a first end, a second source/drain region at a second end, and a channel body disposed between the first end and the second end, wherein the channel body has a thickness that is greater than or about 5% less than a thickness of at least a portion of the first source/drain region and the second source/drain region.

### Claim 11

A method of forming a vertical cell array transistor (VCAT), comprising:
etching a substrate to form one or more shallow trench isolations and a plurality of vertically extending channels;
depositing a first protective dielectric material in the shallow trench isolation adjacent to a first source/drain region at a first end of the vertically extending channel;
depositing a sacrificial dielectric material over the first protective dielectric material;
depositing a second protective dielectric material over the sacrificial dielectric material adjacent to a second source/drain region at a second end of the vertically extending channel;
removing the sacrificial dielectric material; and
reducing a thickness of a channel body of the one or more of the vertically extending channels, wherein the channel body is disposed between the first source/drain region and the second source/drain region.

### Claim 12 (depends on 11)

The method of claim 11, further comprising etching the second protective dielectric material to form a support mesh.

### Claim 13 (depends on 11)

The method of claim 11, further comprising reducing a thickness of a portion of the first source/drain region, the second source/drain region, or a combination thereof.

### Claim 14 (depends on 11)

The method of claim 11, wherein the first protective dielectric material is deposited extending from the first end to a height that is generally coplanar with a top surface of the first source/drain region or less.

### Claim 15 (depends on 14)

The method of claim 14, wherein the sacrificial dielectric material is deposited extending from a top surface of the first protective dielectric material to a height that is greater than or generally coplanar with a bottom surface of the second source/drain region.

### Claim 16 (depends on 15)

The method of claim 15, wherein the second protective dielectric material is deposited extending from a height that is greater than or generally coplanar with the bottom surface of the second source/drain region to the second end of the vertically extending channel.

### Claim 17 (depends on 11)

The method of claim 11, further comprising removing the first protective dielectric material and the second protective dielectric material, and depositing a gate dielectric layer and a gate metal around a perimeter of the one or more shallow trench isolations.

### Claim 18 (depends on 17)

The method of claim 17, wherein greater the channel body is reduced in thickness by greater than or about 5%.

### Claim 19 (depends on 11)

The method of claim 11, wherein reducing the thickness of the channel body comprises a selective silicon etch, an oxidation and wet etch, or a combination thereof.

### Claim 20 (depends on 12)

The method of claim 12, wherein the sacrificial dielectric material comprises a material that can be selectively etched without etching the first protective dielectric material and the second protective dielectric material.