# US 2025/0098147 A1 · Semiconductor device

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- Number: US 2025/0098147 A1
- Document ID: US20250098147A1
- Status: Published application
- Kind: A1
- Application number: 18/828,170
- Filed: 2024-09-09
- Published: 2025-03-20
- Earliest claimed: 2023-09-19
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Sunghwan JANG; Wonhee CHOI; Jinbum KIM; Daejin NAM; Hyojin PARK; Sunguk JANG
- Web page: https://patentgrep.com/patent/US20250098147A1

## CPC

- H10B 12/315: {with the capacitor higher than a bit line}
- H10B 12/05: {Making the transistor}
- H10D 30/6728: {Vertical TFTs}
- H10B 12/488: {Word lines}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a substrate, a bit line extending in a first direction on the substrate, a first vertical channel pattern and a second vertical channel pattern on the bit line, a back gate electrode between the first vertical channel pattern and the second vertical channel pattern and extending in a second direction perpendicular to the first direction across the bit line, a first word line extending in the second direction from one side of the first vertical channel pattern, a second word line extending in the second direction from other side of the second vertical channel pattern, and a contact pattern connected to each of the first vertical channel pattern and the second vertical channel pattern. When viewed from a cross-sectional view, each of the first vertical channel pattern and the second vertical channel pattern have a trapezoidal shape with the long sides facing each other.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate;
a bit line extending in a first direction on the substrate;
a first vertical channel pattern and a second vertical channel pattern on the bit line;
a back gate electrode between the first vertical channel pattern and the second vertical channel pattern and extending in a second direction perpendicular to the first direction across the bit line;
a first word line extending in the second direction from one side of the first vertical channel pattern;
a second word line extending in the second direction from other side of the second vertical channel pattern; and
a contact pattern connected to each of the first vertical channel pattern and the second vertical channel pattern,
wherein, when viewed from a cross-sectional view, each of the first vertical channel pattern and the second vertical channel pattern have a trapezoidal shape with the long sides facing each other.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein each of the first vertical channel pattern and the second vertical channel pattern includes a silicon (Si) epitaxial growth layer.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein
each of the first vertical channel pattern and the second vertical channel pattern has a top facet at a topmost portion of an inclined sidewall and a bottom facet at a bottommost portion of an inclined sidewall,
the first word line is faces a short side of the first vertical channel pattern without facing the top and bottom facets of the first vertical channel pattern, and
the second word line is faces a short side of the second vertical channel pattern without facing the top and bottom facets of the second vertical channel pattern.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the top facet of each of the first vertical channel pattern and the second vertical channel pattern contacts the contact pattern.

### Claim 5 (depends on 3)

The semiconductor device of claim 3, wherein the bottom facet of each of the first vertical channel pattern and the second vertical channel pattern contacts the bit line.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein, when viewed from a plan view,
the first word line has a plurality of first protrusions protruding between a plurality of the first vertical channel patterns, and
the second word line has a plurality of second protrusions protruding between a plurality of the second vertical channel patterns.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein
the first word line and the plurality of first protrusions face the plurality of first vertical channel patterns on three different planes to form a tri-gate structure, and
the second word line and the plurality of second protrusions face the plurality of second vertical channel patterns on three different planes to form a tri-gate structure.

### Claim 8 (depends on 6)

The semiconductor device of claim 6, wherein the plurality of first protrusions of the first word line and the plurality of second protrusions of the second word line have a mirror image symmetrical structure with respect to the back gate electrode.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, further comprising
a gate insulating pattern between the first and second word lines and the corresponding first and second vertical channel patterns,
wherein the gate insulating pattern extends to top surfaces of the first and second word lines.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, further comprising a data storage pattern connected to the contact pattern.

### Claim 11

A semiconductor device comprising:
a substrate;
a bit line extending in a first direction on the substrate;
a pair of vertical channel patterns on the bit line;
a back gate electrode between the pair of vertical channel patterns and extending in a second direction perpendicular to the first direction across the bit line;
a pair of word lines outside the pair of vertical channel patterns and extending in the second direction; and
contact patterns connected to each of the pair of vertical channel patterns,
wherein each of the pair of vertical channel patterns is an epitaxially grown layer having a top facet at a topmost portion of an inclined sidewall and a bottom facet at a bottommost portion of an inclined sidewall.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the pair of vertical channel patterns have a mirror image symmetrical structure with respect to the back gate electrode.

### Claim 13 (depends on 11)

The semiconductor device of claim 11, wherein, when viewed from a cross-sectional view,
each of the pair of vertical channel patterns has a trapezoidal shape,
the back gate electrode faces a long side of the trapezoidal shape, and
the pair of word lines face a short side of the trapezoidal shape.

### Claim 14 (depends on 11)

The semiconductor device of claim 11, wherein
a level of a topmost surface of the pair of vertical channel patterns is higher than a level of a topmost surface of the pair of word lines, and
a level of a bottommost surface of the pair of vertical channel patterns is lower than a level of a bottommost surface of the pair of word lines.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein
the level of a topmost surface of the pair of word lines is higher than a level of a topmost surface of the back gate electrode, and
the level of the bottommost surface of the pair of word lines is lower than a level of a bottommost surface of the back gate electrode.

### Claim 16

A semiconductor device comprising:
a substrate;
a bit line extending in a first direction on the substrate;
a first vertical channel pattern and a second vertical channel pattern on the bit line;
a back gate electrode between the first and second vertical channel patterns and extending in a second direction perpendicular to the first direction across the bit line;
a first word line extending in the second direction from one side of the first vertical channel pattern;
a second word line extending in the second direction from other side of the second vertical channel pattern;
a gate insulating pattern conformally between the first and second vertical channel patterns and the first and second word lines and on top surfaces of the first and second word lines;
a contact pattern connected to each of the first vertical channel pattern and the second vertical channel pattern; and
a data storage pattern connected to the contact pattern,
wherein, when viewed from a cross-sectional view, each of the first vertical channel pattern and the second vertical channel pattern has a trapezoidal shape that is a mirror image symmetrical structure with respect to the back gate electrode.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein
each of the first vertical channel pattern and the second vertical channel pattern has a top facet at a topmost portion of an inclined sidewall and a bottom facet at a bottommost portion of an inclined sidewall,
the top facet of each of the first vertical channel pattern and the second vertical channel pattern contacts the contact pattern, and
the bottom facet of each of the first vertical channel pattern and the second vertical channel pattern contacts the bit line.

### Claim 18 (depends on 16)

The semiconductor device of claim 16, wherein, when viewed from a plan view,
the first word line has a plurality of first protrusions protruding between a plurality of the first vertical channel patterns, and
the second word line has a plurality of second protrusions protruding between a plurality of the second vertical channel patterns.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein
the first word line and the plurality of first protrusions face the plurality of first vertical channel patterns on three different planes to form a tri-gate structure, and
the second word line and the plurality of second protrusions face the plurality of second vertical channel patterns on three different planes to form a tri-gate structure.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein the plurality of first protrusions of the first word line and the plurality of second protrusions of the second word line have a mirror image symmetrical structure with respect to the back gate electrode.