# US 2025/0097401 A1 · Display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0097401 A1 - Document ID: US20250097401A1 - Status: Published application - Kind: A1 - Application number: 18/829,888 - Filed: 2024-09-10 - Published: 2025-03-20 - Earliest claimed: 2023-09-19 - Assignees: Samsung Display Co., Ltd. - Applicants: Samsung Display Co., Ltd. - Inventors: Young Soo HWANG; Seong Joo LEE - Web page: https://patentgrep.com/patent/US20250097401A1 ## CPC - H04N 13/359: Switching between monoscopic and stereoscopic modes - G02F 1/13306: {Circuit arrangements or driving methods for the control of single liquid crystal cells (G02F1/132, G02F1/133382 take precedence)} - H04N 13/305: using lenticular lenses, e.g. arrangements of cylindrical lenses - H04N 13/315: the parallax barriers being time-variant - H04N 13/351: for displaying simultaneously - H04N 13/398: Synchronisation thereof; Control thereof - G09G 3/003: {to produce spatial visual effects} - G09G 2320/0257: Reduction of after-image effects - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A display device includes: pixels; a first electrode located on the pixels; a liquid crystal layer located on the first electrode; a second electrode located on the liquid crystal layer; a lens array located on the second electrode; and a control circuit including a first node electrically connected to the first electrode and a second node electrically connected to the second electrode. In a first mode, the control circuit applies a first node voltage to the first node, and applies, to the second node, a second node voltage which alternates a high level higher than a voltage level of the first node voltage and a low level lower than the voltage level of the first node voltage. In a second mode, the control circuit allows the first node and the second node to be short-circuited. ## Claims ### Claim 1 A display device comprising: a first electrode; a liquid crystal layer located on the first electrode; a second electrode located on the liquid crystal layer; a lens array located on the second electrode; and a control circuit including a first node electrically connected to the first electrode and a second node electrically connected to the second electrode, wherein, in a first mode, the control circuit is configured to apply a first node voltage to the first node, and is configured to apply a second node voltage to the second node, wherein the second node voltage alternates between a high level voltage higher than a voltage level of the first node voltage and a low level voltage lower than the voltage level of the first node voltage, and wherein, in a second mode, the control circuit is configured to short-circuit the first node and the second node. ### Claim 2 (depends on 1) The display device of claim 1, wherein the first mode is a three-dimensional (3D) mode, and the second mode is a two-dimensional (2D) mode. ### Claim 3 (depends on 1) The display device of claim 1, wherein the control circuit includes: a first resistor including a first electrode configured to receive a first voltage; a second resistor including a first electrode configured to receive the first voltage; a first transistor including a base/gate electrode electrically connected to a second electrode of the first resistor, a first electrode electrically connected to the second node, and a second electrode electrically connected to the first node; and a second transistor including a base/gate electrode electrically connected to a second electrode of the second resistor, a first electrode configured to receive a second voltage, and a second electrode electrically connected to the second node. ### Claim 4 (depends on 3) The display device of claim 3, wherein each of the first transistor and the second transistor is a Bipolar Junction Transistor (BJT). ### Claim 5 (depends on 4) The display device of claim 4, wherein the first transistor is a PNP transistor, and the second transistor is an NPN transistor. ### Claim 6 (depends on 5) The display device of claim 5, wherein the first node is connected to a ground. ### Claim 7 (depends on 5) The display device of claim 5, wherein the first node is connected to a voltage source different from a ground. ### Claim 8 (depends on 7) The display device of claim 7, wherein the voltage source is configured to supply a voltage having a voltage level higher than a voltage level of the ground in the first mode and the second mode. ### Claim 9 (depends on 8) The display device of claim 8, wherein the low level voltage of the second node voltage is equal to the voltage level of the ground, and wherein the voltage level of the voltage supplied from the voltage source is equal to the voltage level of the ground in a turn-off state of the display device. ### Claim 10 (depends on 3) The display device of claim 3, wherein the first voltage maintains a high level voltage in the first mode and maintains a low level voltage in the second mode. ### Claim 11 A display device comprising: a first electrode; a liquid crystal layer on the first electrode; a second electrode on the liquid crystal layer; a first node electrically connected to the first electrode; a second node electrically connected to the second electrode; and a control circuit, wherein the control circuit includes: a first transistor including a base/gate electrode configured to receive a first voltage, a first electrode configured to receive a second voltage, and a second electrode electrically connected to the second node, a second transistor including a base/gate electrode configured to receive a third voltage, a first electrode configured to receive the second voltage, and a second electrode electrically connected to the second node; and a third transistor including a base/gate electrode configured to receive the third voltage, a first electrode electrically connected to the second node, and a second electrode electrically connected to the first node, wherein, in a first mode, the control circuit is configured to apply a first node voltage to the first node, and is configured to apply a second node voltage to the second node, wherein the second node voltage alternates between a high level voltage higher than a voltage level of the first node voltage and a low level voltage lower than the voltage level of the first node voltage, and wherein, in a second mode, the control circuit is configured to short-circuit the first node and the second node. ### Claim 12 (depends on 11) The display device of claim 11, wherein the control circuit further includes: a first inverter including an input terminal configured to receive the second voltage; and a second inverter including an input terminal electrically connected to an output terminal of the first inverter, and an output terminal electrically connected to the first electrode of the first transistor and the first electrode of the second transistor. ### Claim 13 (depends on 11) The display device of claim 11, wherein each of the first transistor, the second transistor, and the third transistor is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). ### Claim 14 (depends on 13) The display device of claim 13, wherein the first transistor is an NMOS transistor, the second transistor is a PMOS transistor, and the third transistor is an NMOS transistor. ### Claim 15 (depends on 14) The display device of claim 14, wherein the first node is electrically connected to a ground. ### Claim 16 (depends on 14) The display device of claim 14, wherein the first node is electrically connected to a voltage source different from a ground. ### Claim 17 (depends on 16) The display device of claim 16, wherein the voltage source configured to supply a voltage having a voltage level higher than a voltage level of the ground in the first mode and the second mode. ### Claim 18 (depends on 17) The display device of claim 17, wherein the low level voltage of the second node voltage is equal to the voltage level of the ground, and wherein the voltage level of the voltage supplied from the voltage source is equal to the voltage level of the ground in a turn-off state of the display device. ### Claim 19 (depends on 14) The display device of claim 14, wherein the third voltage is a reversed voltage of the first voltage. ### Claim 20 A display device comprising: a first electrode; a liquid crystal layer on the first electrode; a second electrode on the liquid crystal layer; a first node electrically connected to the first electrode; a second node electrically connected to the second electrode; and a control circuit, wherein the control circuit includes: a first transistor including a base/gate electrode configured to receive a first voltage, a first electrode configured to receive a second voltage, and a second electrode electrically connected to the second node, a second transistor including a base/gate electrode configured to receive a third voltage, a first electrode configured to receive the second voltage, and a second electrode electrically connected to the second node; and a third transistor including a base/gate electrode configured to receive the third voltage, a first electrode electrically connected to the second node, and a second electrode electrically connected to the first node, wherein, in a first mode, the control circuit is configured to apply a first node voltage to the first node, and is configured to apply a second node voltage to the second node, wherein the second node voltage alternates between a high level voltage higher than a voltage level of the first node voltage and a low level voltage lower than the voltage level of the first node voltage, and wherein, in a second mode, the control circuit is configured to short-circuit the first node and the second node, and wherein the first voltage maintains a high level voltage in the first mode and maintains a low level voltage in the second mode.