# US 2025/0097019 A1 · Coherent key management across multiple chiplets

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- Number: US 2025/0097019 A1
- Document ID: US20250097019A1
- Status: Published application
- Kind: A1
- Application number: 18/468,666
- Filed: 2023-09-15
- Published: 2025-03-20
- Earliest claimed: 2023-09-15
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Rengarajan RAGAVAN; Arun MENON; Samar ASBE; Aseem BRAHMA; Shivaprasad HONGAL; Changjian GAO; Denis POCHUEV
- Web page: https://patentgrep.com/patent/US20250097019A1

## CPC

- G06F 21/572: {Secure firmware programming, e.g. of basic input output system [BIOS]}
- H04L 9/0838: {Key agreement, i.e. key establishment technique in which a shared key is derived by parties as a function of information contributed by, or associated with, each of these (network architectures or network communication protocols for key exchange in a packet data network H04L63/061)}
- G06F 21/445: {by mutual authentication, e.g. between devices or programs}
- G06F 21/57: Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
- G06F 21/72: in cryptographic circuits
- H04L 9/0822: {using key encryption key}
- H04L 9/0866: {involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics}
- H04L 9/0877: {using additional device, e.g. trusted platform module [TPM], smartcard, USB or hardware security module [HSM]}
- H04L 9/0897: {involving additional devices, e.g. trusted platform module [TPM], smartcard or USB}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

Systems and techniques are provided for establishing a connection. For instance, a process may include receiving, at a first chiplet root of trust (C-ROT) of a first chiplet of a plurality of chiplets, a request for a cryptographic key; generating, by the first C-ROT, the cryptographic key; wrapping, by the first C-ROT, the cryptographic key using a wrapping key to generate a wrapped cryptographic key; outputting, by the first C-ROT, the wrapped cryptographic key; receiving the wrapped cryptographic key at a second C-ROT of a second chiplet of the plurality of chiplets; unwrapping, by the second C-ROT, the wrapped cryptographic key using the wrapping key; and performing, by the second C-ROT, an operation based on the cryptographic key.

## Claims

### Claim 1

An electronic device, comprising:
a memory system comprising instructions; and
a processor system coupled to the memory system, the processor system including a plurality of chiplets, wherein the processor system is configured to:
receive, at a first chiplet root of trust (C-ROT) of a first chiplet of the plurality of chiplets, a request for a cryptographic key;
generate, by the first C-ROT, the cryptographic key;
wrap, by the first C-ROT, the cryptographic key using a wrapping key to generate a wrapped cryptographic key;
output, by the first C-ROT, the wrapped cryptographic key;
receive the wrapped cryptographic key at a second chiplet of the plurality of chiplets;
unwrap the wrapped cryptographic key at the second chiplet using the wrapping key; and
perform, by the second C-ROT, an operation based on the cryptographic key.

### Claim 2 (depends on 1)

The electronic device of claim 1, wherein, to wrap the cryptographic key, the processor system is configured to encrypt, by the first C-ROT, the cryptographic key using the wrapping key.

### Claim 3 (depends on 1)

The electronic device of claim 1, wherein the cryptographic key is generated based on a common pairing key.

### Claim 4 (depends on 3)

The electronic device of claim 3, wherein the common pairing key is provisioned to two or more C-RoTs of the plurality of chiplets.

### Claim 5 (depends on 1)

The electronic device of claim 1, wherein the wrapped cryptographic key is received at a cryptographic endpoint associated with the second C-RoT.

### Claim 6 (depends on 5)

The electronic device of claim 5, wherein the wrapped cryptographic key is unwrapped by the cryptographic endpoint.

### Claim 7 (depends on 1)

The electronic device of claim 1, wherein the wrapping key comprises one of a common transport key or a key swap key.

### Claim 8 (depends on 7)

The electronic device of claim 7, wherein the wrapping key comprises a key swap key and wherein, to output the wrapped cryptographic key, the processor system is configured to store the wrapped cryptographic key in the memory system, and wherein the wrapped cryptographic key is received from the memory system.

### Claim 9 (depends on 1)

The electronic device of claim 1, wherein the wrapping key is provisioned to C-RoTs of the plurality of chiplets.

### Claim 10 (depends on 1)

The electronic device of claim 1, wherein the wrapping key is provisioned during a boot procedure of the processor system.

### Claim 11

A method for secure processing, comprising:
receiving, at a first chiplet root of trust (C-ROT) of a first chiplet of a plurality of chiplets, a request for a cryptographic key;
generating, by the first C-ROT, the cryptographic key;
wrapping, by the first C-ROT, the cryptographic key using a wrapping key to generate a wrapped cryptographic key;
outputting, by the first C-ROT, the wrapped cryptographic key;
receiving the wrapped cryptographic key at a second chiplet of the plurality of chiplets;
unwrapping, the wrapped cryptographic key at the second chiplet using the wrapping key; and
performing, by the second C-ROT, an operation based on the cryptographic key.

### Claim 12 (depends on 11)

The method of claim 11, wherein wrapping the cryptographic key comprises encrypting, by the first C-ROT, the cryptographic key using the wrapping key.

### Claim 13 (depends on 11)

The method of claim 11, wherein the cryptographic key is generated based on a common pairing key.

### Claim 14 (depends on 13)

The method of claim 13, wherein the common pairing key is provisioned to two or more C-RoTs of the plurality of chiplets.

### Claim 15 (depends on 11)

The method of claim 11, wherein the wrapped cryptographic key is received at a cryptographic endpoint associated with the second C-RoT.

### Claim 16 (depends on 15)

The method of claim 15, wherein the wrapped cryptographic key is unwrapped by the cryptographic endpoint.

### Claim 17 (depends on 11)

The method of claim 11, wherein the wrapping key comprises one of a common transport key or a key swap key.

### Claim 18 (depends on 17)

The method of claim 17, wherein the wrapping key comprises a key swap key and wherein outputting the wrapped cryptographic key comprises storing the wrapped cryptographic key in a memory system, and wherein the wrapped cryptographic key is received from the memory system.

### Claim 19 (depends on 11)

The method of claim 11, wherein the wrapping key is provisioned to C-RoTs of the plurality of chiplets.

### Claim 20 (depends on 11)

The method of claim 11, wherein the wrapping key is provisioned during a boot procedure of the plurality of chiplets.

### Claim 21

A non-transitory computer-readable medium having stored thereon instructions that, when executed by a processor system, cause the processor system to:
receive, at a first chiplet root of trust (C-RoT) of a first chiplet of a plurality of chiplets, a request for a cryptographic key;
generate, by the first C-ROT, the cryptographic key;
wrap, by the first C-ROT, the cryptographic key using a wrapping key to generate a wrapped cryptographic key;
output, by the first C-RoT, the wrapped cryptographic key;
receive the wrapped cryptographic key at a second chiplet of the plurality of chiplets;
unwrap the wrapped cryptographic key at the second chiplet using the wrapping key; and
perform, by the second C-ROT, an operation based on the cryptographic key.

### Claim 22 (depends on 21)

The non-transitory computer-readable medium of claim 21, wherein, to wrap the cryptographic key, the instructions further cause the processor system to cryptographically encrypting, by the first C-ROT, the cryptographic key using the wrapping key.

### Claim 23 (depends on 21)

The non-transitory computer-readable medium of claim 21, wherein the cryptographic key is generated based on a common pairing key.

### Claim 24 (depends on 23)

The non-transitory computer-readable medium of claim 23, wherein the common pairing key is provisioned to two or more C-RoTs of the plurality of chiplets.

### Claim 25 (depends on 21)

The non-transitory computer-readable medium of claim 21, wherein the wrapped cryptographic key is received at a cryptographic endpoint associated with the second C-ROT.

### Claim 26 (depends on 25)

The non-transitory computer-readable medium of claim 25, wherein the wrapped cryptographic key is unwrapped by the cryptographic endpoint.

### Claim 27 (depends on 21)

The non-transitory computer-readable medium of claim 21, wherein the wrapping key comprises one of a common transport key or a key swap key.

### Claim 28 (depends on 27)

The non-transitory computer-readable medium of claim 27, wherein the wrapping key comprises a key swap key and wherein, to output the wrapped cryptographic key, the instructions cause the processor system to store the wrapped cryptographic key in a memory system, and wherein the wrapped cryptographic key is received from the memory system.

### Claim 29 (depends on 21)

The non-transitory computer-readable medium of claim 21, wherein the wrapping key is provisioned to C-RoTs of the plurality of chiplets.

### Claim 30 (depends on 21)

The non-transitory computer-readable medium of claim 21, wherein the wrapping key is provisioned during a boot procedure of the plurality of chiplets.