# US 2025/0096937 A1 · Configuring arbitrary jumps in a linear feedback shift register in wireless communications > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0096937 A1 - Document ID: US20250096937A1 - Status: Published application - Kind: A1 - Application number: 18/470,172 - Filed: 2023-09-19 - Published: 2025-03-20 - Earliest claimed: 2023-09-19 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Dinesh DHARMARAJU; Anthony FANOUS; David HOYLE - Web page: https://patentgrep.com/patent/US20250096937A1 ## CPC - H04L 1/0073: {Special arrangements for feedback channel} - G06F 7/584: {using finite field arithmetic, e.g. using a linear feedback shift register} - H04J 13/0029: {Gold} - H04L 1/0016: {involving special memory structures, e.g. look-up tables} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04J: MULTIPLEX COMMUNICATION (transmission in general H04B; peculiar to transmission of digital information H04L5/00; systems for the simultaneous or sequential transmission of more than one television signal H04N7/08; in exchanges H04Q11/00; stereophonic systems H04S) ## Abstract Aspects described herein relate to selecting a base representation for an advance offset of a shift register sequence, generating the shift register sequence corresponding to the advance offset based at least in part on the base representation, and processing a signal based at least in part on the shift register sequence. ## Claims ### Claim 1 An apparatus for wireless communication, comprising: a transceiver; one or more memories configured to, individually or in combination, store instructions; and one or more processors communicatively coupled with the one or more memories, wherein the one or more processors are, individually or in combination, configured to execute the instructions to cause the apparatus to: select a base representation for expressing an advance offset value for generating a shift register sequence to achieve jumps between values of the shift register sequence; generate, based on the advance offset value, the shift register sequence; and process a signal based at least in part on the shift register sequence. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the one or more processors are, individually or in combination, configured to execute the instructions to cause the apparatus to select the base representation based at least in part on a processor specification of the apparatus. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the one or more processors are, individually or in combination, configured to execute the instructions to cause the apparatus to compute a number of Galois multiplies for a Galois jump for each state in the shift register sequence, wherein the one or more processors are, individually or in combination, configured to execute the instructions to cause the apparatus to select the base representation further based at least in part on the number of Galois multiplies using the base representation complying with the processor specification of the device. ### Claim 4 (depends on 2) The apparatus of claim 2, wherein the one or more processors are, individually or in combination, configured to execute the instructions to cause the apparatus to select the base representation further based on a timeline specification of a wireless communication technology. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the one or more processors are, individually or in combination, configured to execute the instructions to cause the apparatus to select the base representation based at least in part on a memory specification of the apparatus. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the one or more processors are, individually or in combination, configured to execute the instructions to cause the apparatus to compute a lookup table size using the base representation for the shift register sequence, wherein the one or more processors are, individually or in combination, configured to execute the instructions to cause the apparatus to select the base representation further based at least in part on the lookup table size complying with a memory specification of the apparatus. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the base representation is based on a modular structure. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein the one or more processors are, individually or in combination, configured to execute the instructions to cause the apparatus to process the signal at least in part by scrambling the signal based at least in part on the shift register sequence. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the one or more processors are, individually or in combination, configured to execute the instructions to cause the apparatus to process the signal at least in part by descrambling the signal based at least in part on the shift register sequence. ### Claim 10 A method for wireless communication by a device, comprising: selecting a base representation for expressing an advance offset value for generating a shift register sequence to achieve jumps between values of the shift register sequence; generating, based on the advance offset value, the shift register sequence; and processing a signal based at least in part on the shift register sequence. ### Claim 11 (depends on 10) The method of claim 10, wherein selecting the base representation is based at least in part on a processor specification of the device. ### Claim 12 (depends on 11) The method of claim 11, further comprising computing a number of Galois multiplies for a Galois jump for each state in the shift register sequence, wherein selecting the base representation is further based at least in part on the number of Galois multiplies using the base representation complying with the processor specification of the device. ### Claim 13 (depends on 11) The method of claim 11, wherein selecting the base representation is further based on a timeline specification of a wireless communication technology. ### Claim 14 (depends on 10) The method of claim 10, wherein selecting the base representation is based at least in part on a memory specification of the device. ### Claim 15 (depends on 10) The method of claim 10, further comprising computing a lookup table size using the base representation for the shift register sequence, wherein selecting the base representation is further based at least in part on the lookup table size complying with a memory specification of the device. ### Claim 16 (depends on 10) The method of claim 10, wherein the base representation is based on a modular structure. ### Claim 17 (depends on 10) The method of claim 10, wherein processing the signal includes scrambling the signal based at least in part on the shift register sequence. ### Claim 18 (depends on 10) The method of claim 10, wherein processing the signal includes descrambling the signal based at least in part on the shift register sequence. ### Claim 19 One or more non-transitory computer-readable media including code executable by one or more processors for wireless communication by a device, the code including code for: selecting a base representation for expressing an advance offset value for generating a shift register sequence to achieve jumps between values of the shift register sequence; generating, based on the advance offset value, the shift register sequence; and processing a signal based at least in part on the shift register sequence. ### Claim 20 (depends on 19) The one or more non-transitory computer-readable media of claim 19, wherein selecting the base representation is based at least in part on a processor specification of the device.