Delay-locked loop (dll) with binary search locking and dead clock detection
AssigneeIntel Corporation
InventorsNicolas Wainstein, Eugene Avner
Life of this patent
Estimating the term…
Abstract
A system includes memory and at least one processor coupled to the memory and configured to receive a phase detector (PD) error signal. The PD error signal indicates a leading clock signal of at least two clock signals. The at least two clock signals are generated based on an input clock signal and a voltage control signal. The at least one processor receives a toggling signal indicating whether one of the at least two clock signals is toggling between clock cycles of the input clock signal. A code value is generated based on the PD error signal and the toggling signal. The at least one processor causes generation of the voltage control signal based on the code value.
Claims20
An apparatus comprising:
- a voltage-controlled delay line (VCDL) circuit to generate a plurality of output clock signals based on an input clock signal and a voltage control signal;
- a phase detector (PD) circuit to generate a PD error signal;
- and
- a controller circuit to receive the PD error signal and a toggling signal and to output a code value based on the PD error signal and the toggling signal.
A system comprising:
- memory;
- and
- at least one processor coupled to the memory, the at least one processor to:
- receive a phase detector (PD) error signal, the PD error signal indicating a leading clock signal of at least two clock signals, the at least two clock signals generated based on an input clock signal and a voltage control signal;
- receive a toggling signal, the toggling signal indicating whether one of the at least two clock signals is toggling between clock cycles of the input clock signal;
- generate a code value based on the PD error signal and the toggling signal;
- and
- cause generation of the voltage control signal based on the code value.
A method comprising:
- receiving a phase detector (PD) error signal, the PD error signal indicating a leading clock signal of at least two clock signals, the at least two clock signals generated based on an input clock signal and a voltage control signal;
- receiving a toggling signal, the toggling signal indicating whether one of the at least two clock signals is toggling between clock cycles of the input clock signal;
- generating a code value based on the PD error signal and the toggling signal;
- and
- generating the voltage control signal based on the code value.
Dependencies are inferred from the claim text.