# US 2025/0096558 A1 · Semiconductor device structure and method of manufacturing the same

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- Number: US 2025/0096558 A1
- Document ID: US20250096558A1
- Status: Published application
- Kind: A1
- Application number: 18/573,406
- Filed: 2022-11-15
- Published: 2025-03-20
- Earliest claimed: 2022-11-15
- Assignees: Innoscience (Suzhou) Semiconductor Co., Ltd.
- Applicants: Innoscience (Suzhou) Semiconductor Co., Ltd.
- Inventors: Chang CHEN; Xiaoming LIU; Xinyu LI
- Web page: https://patentgrep.com/patent/US20250096558A1

## CPC

- H02H 9/046: {responsive to excess voltage appearing at terminals of integrated circuits}
- H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 84/0123: {Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs}
- H10D 84/813: {Combinations of field-effect devices and capacitor only}
- H10D 84/82: of only field-effect components
- H10D 62/343: {Gate regions of field-effect devices having PN junction gates}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 84/05: using Group III-V technology
- H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a first transistor and a clamping device. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The first transistor is disposed on the second nitride semiconductor layer. The first transistor includes a first control electrode, a first current electrode and a second current electrode. The clamping device is disposed on the second nitride semiconductor layer and electrically coupled with the first transistor. The clamping device includes a second transistor and a third transistor electrically coupled with the second transistor. The clamping device is electrically coupled with the first current electrode and the second current electrode of the first transistor.

## Claims

### Claim 1

A semiconductor device structure, comprising:
a substrate;
a first nitride semiconductor layer disposed on the substrate;
a second nitride semiconductor layer disposed on the first nitride semiconductor layer;
a first transistor disposed on the second nitride semiconductor layer, wherein the first transistor comprises a first control electrode, a first current electrode and a second current electrode; and
a clamping device disposed on the second nitride semiconductor layer and electrically coupled with the first transistor, wherein the clamping device comprises a second transistor and a third transistor electrically coupled with the second transistor, and the clamping device is electrically coupled with the first current electrode and the second current electrode of the first transistor.

### Claim 2 (depends on 1)

The semiconductor device structure of claim 1, wherein
the second transistor comprises a second control electrode and a third current electrode,
the third transistor comprises a third control electrode and a fourth current electrode, and
a first potential midpoint is electrically coupled with the first control electrode, the third current electrode, and the fourth current electrode.

### Claim 3 (depends on 2)

The semiconductor device structure of claim 2, wherein a first dimension of the first control electrode is different from a second dimension of the second control electrode.

### Claim 4 (depends on 2)

The semiconductor device structure of claim 2, wherein the first dimension of the first control electrode is greater than the second dimension of the second control electrode.

### Claim 5 (depends on 2)

The semiconductor device structure of claim 2, wherein a first distance between the first control electrode and the first current electrode of the first transistor is different from a second distance between the second control electrode and the third current electrode of the second transistor.

### Claim 6 (depends on 5)

The semiconductor device structure of claim 5, wherein the first distance between the first control electrode and the first current electrode of the first transistor is greater than the second distance between the second control electrode and the third current electrode.

### Claim 7 (depends on 2)

The semiconductor device structure of claim 2, wherein
the clamping device further comprises a fourth transistor and a fifth transistor,
the fourth transistor comprises a fourth control electrode,
the fifth transistor comprises a fifth control electrode, and
the first potential midpoint is electrically coupled with the fourth control electrode and the fifth control electrode.

### Claim 8 (depends on 7)

The semiconductor device structure of claim 7, wherein
the fourth transistor comprises a seventh current electrode, and
a second potential midpoint is electrically coupled with the seventh current electrode of the fourth transistor and the second current electrode of the first transistor.

### Claim 9 (depends on 7)

The semiconductor device structure of claim 7, wherein the fourth transistor comprises an eighth current electrode electrically coupled with the second control electrode of the second transistor.

### Claim 10 (depends on 7)

The semiconductor device structure of claim 7, wherein
the fifth transistor comprises a ninth current electrode, and
a third potential midpoint is electrically coupled with the nine current electrode of the fifth transistor and the first current electrode of the first transistor.

### Claim 11 (depends on 7)

The semiconductor device structure of claim 7, wherein the fifth transistor comprises a tenth current electrode electrically coupled with the third control electrode of the third transistor.

### Claim 12 (depends on 7)

The semiconductor device structure of claim 7, wherein the first dimension of the first control electrode is different from a third dimension of the fourth control electrode.

### Claim 13 (depends on 7)

The semiconductor device structure of claim 7, wherein the first dimension of the first control electrode is greater than the third dimension of the fourth control electrode.

### Claim 14 (depends on 1)

The semiconductor device structure of claim 1, further comprising:
a third nitride semiconductor layer doped with impurities and disposed between the first control electrode and the second nitride semiconductor layer.

### Claim 15 (depends on 1)

The semiconductor device structure of claim 1, further comprising:
a capacitor electrically connected to the second current electrode.

### Claim 16

A method of manufacturing a semiconductor device structure, comprising:
providing a substrate;
forming a first nitride semiconductor layer on the substrate;
forming a second nitride semiconductor layer on the first nitride semiconductor layer;
forming a first transistor on the second nitride semiconductor layer, wherein the first transistor comprises a first control electrode, a first current electrode and a second current electrode; and
forming a clamping device on the second nitride semiconductor layer, wherein the clamping device comprises a second transistor and a third transistor electrically coupled with the second transistor, and the clamping device is electrically coupled with the first current electrode and the second current electrode of the first transistor.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
forming a third nitride semiconductor layer doped with impurities, wherein the third nitride semiconductor layer is located between the first control electrode and the second nitride semiconductor layer.

### Claim 18 (depends on 16)

The method of claim 16, further comprising:
forming a capacitor electrically connected to the first transistor.

### Claim 19 (depends on 16)

The method of claim 16, wherein
the second transistor comprises a second control electrode and a third current electrode,
the third transistor comprises a third control electrode and a fourth current electrode, and
a first potential midpoint is electrically coupled with the first control electrode, the third current electrode, and the fourth electrode.

### Claim 20 (depends on 16)

The method of claim 16, wherein a first dimension of the first control electrode is different from a second dimension of the second control electrode.

### Claim 21

A semiconductor device structure, comprising:
a substrate;
a first nitride semiconductor layer disposed on the substrate;
a second nitride semiconductor layer disposed on the first nitride semiconductor layer;
a first transistor disposed on the second nitride semiconductor layer, wherein the first transistor comprises a first control electrode, a first current electrode and a second current electrode; and
a clamping device disposed on the second nitride semiconductor layer, wherein the clamping device comprises a second transistor and a third transistor, the second transistor comprises a second control electrode, a third current electrode, and fourth current electrode, the third transistor comprises a third control electrode and a fifth current electrode, and wherein
the third current electrode of the second transistor is coupled with the third control electrode of the third transistor, a first potential midpoint is connected to the fifth current electrode of the third transistor and the first current electrode of the first transistor, and a second potential midpoint is connected to the fourth current electrode of the second transistor and the second current electrode of the first transistor.

### Claim 22 (depends on 21)

The semiconductor device structure of claim 21, wherein a third potential midpoint is connected to the first control electrode of the first transistor and the second control electrode of the second transistor.

### Claim 23 (depends on 21)

The semiconductor device structure of claim 21, wherein a first dimension of the first control electrode is different from a second dimension of the second control electrode.

### Claim 24 (depends on 21)

The semiconductor device structure of claim 21, further comprising:
a third nitride semiconductor layer doped with impurities and disposed between the first control electrode and the second nitride semiconductor layer.

### Claim 25 (depends on 21)

The semiconductor device structure of claim 21, further comprising:
a capacitor electrically connected to the first transistor.