# US 2025/0096218 A1 · Semiconductor package and method of manufacturing the same

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- Number: US 2025/0096218 A1
- Document ID: US20250096218A1
- Status: Published application
- Kind: A1
- Application number: 18/678,643
- Filed: 2024-05-30
- Published: 2025-03-20
- Earliest claimed: 2023-09-15
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Haseob SEONG; Aenee JANG; Dawoon JUNG
- Web page: https://patentgrep.com/patent/US20250096218A1

## CPC

- H10W 90/00: Package configurations
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 74/10: characterised by their shape or disposition
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/20: Configurations of stacked chips
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package including: a base structure including upper and lower surfaces with upper and lower connection pads, the upper connection pad being connected to the lower connection pad; a plurality of first semiconductor chips stacked on the base structure, wherein the plurality of first semiconductor chips includes uppermost and lowermost chips, and wherein each of the plurality of first semiconductor chips includes a first lower and upper pads, and a silicon via connecting the first lower and upper pads; a cover chip, on the uppermost semiconductor chip, including an upper surface with a flat region and an edge region; and an upper dummy chip on the flat region and including an area smaller than an area of the cover chip and a thickness greater than a thickness of the cover chip, wherein the first lower pad of the lowermost chip is connected to the upper connection pad, and wherein the first upper pad of each of the plurality of first semiconductor chips, except for the uppermost chip, is connected to the first lower pad of another first semiconductor chip.

## Claims

### Claim 1

A semiconductor package comprising:
a base structure comprising a lower surface with a lower connection pad thereon, and an upper surface with an upper connection pad thereon, wherein the upper connection pad is connected to the lower connection pad;
a plurality of first semiconductor chips stacked on the base structure in a vertical direction, wherein the plurality of first semiconductor chips comprises an uppermost first semiconductor chip and a lowermost first semiconductor chip, and wherein each of the plurality of first semiconductor chips comprises a first lower pad, a first upper pad, and a through silicon via connecting the first lower pad to the first upper pad;
a cover chip on the plurality of first semiconductor chips, the cover chip comprising an upper surface, wherein the upper surface comprises a flat region and an edge region having a rounded shape, and wherein the edge region is disposed around the flat region; and
an upper dummy chip disposed on the flat region of the cover chip, the upper dummy chip comprising an area smaller than an area of the cover chip and a thickness greater than a thickness of the cover chip,
wherein the first lower pad of the lowermost first semiconductor chip is directly connected to the upper connection pad, and
wherein the first upper pad of each of the plurality of first semiconductor chips, except for the uppermost first semiconductor chip, is directly connected to the first lower pad of another first semiconductor chip, among the plurality of first semiconductor chips, adjacent thereto.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein the base structure further comprises a first area, and wherein each of the plurality of first semiconductor chips comprises a second area smaller than the first area.

### Claim 3 (depends on 2)

The semiconductor package of claim 2, further comprising:
a molding portion disposed on the base structure and surrounding the plurality of first semiconductor chips, the cover chip, and the upper dummy chip.

### Claim 4 (depends on 3)

The semiconductor package of claim 3, wherein an upper surface of the upper dummy chip is substantially coplanar with an upper surface of the molding portion.

### Claim 5 (depends on 1)

The semiconductor package of claim 1,
wherein each of the plurality of first semiconductor chips further comprises:
a first lower insulating layer on a lower surface thereof and surrounding a side surface of the first lower pad; and
a first upper insulating layer disposed on an upper surface thereof and surrounding a side surface of the first upper pad, and
wherein the first upper insulating layer of each the plurality of first semiconductor chips is directly bonded to the first lower insulating layer of another first semiconductor chip, among the plurality of first semiconductor chips, adjacent thereto.

### Claim 6 (depends on 5)

The semiconductor package of claim 5,
wherein the base structure further comprises a bonding insulating layer on the upper surface and surrounding a side surface of the upper connection pad, and
wherein the first lower insulating layer of the lowermost first semiconductor chip is directly bonded to the bonding insulating layer.

### Claim 7 (depends on 1)

The semiconductor package of claim 1,
wherein the cover chip comprises a second semiconductor chip comprising a second lower pad, and
wherein the second lower pad is directly bonded to the first upper pad of the uppermost first semiconductor chip.

### Claim 8 (depends on 7)

The semiconductor package of claim 7, wherein the second semiconductor chip is of the same type as the plurality of first semiconductor chips.

### Claim 9 (depends on 1)

The semiconductor package of claim 1, further comprising:
a second semiconductor chip disposed between the uppermost first semiconductor chip and the cover chip, the second semiconductor chip comprising a second lower pad on a lower surface thereof,
wherein the second lower pad of the second semiconductor chip is directly bonded to the first upper pad of the uppermost first semiconductor chip.

### Claim 10 (depends on 9)

The semiconductor package of claim 9, wherein the cover chip further comprises a lower dummy chip.

### Claim 11 (depends on 1)

The semiconductor package of claim 1, wherein the base structure further comprises an interposer substrate comprising an internal wiring layer connecting the lower connection pad to the upper connection pad.

### Claim 12 (depends on 1)

The semiconductor package of claim 1, wherein the base structure further comprises a lower semiconductor chip comprising a through-via connecting the lower connection pad to the upper connection pad.

### Claim 13 (depends on 12)

The semiconductor package of claim 12, wherein each of the plurality of first semiconductor chips comprises a memory chip, and
wherein the lower semiconductor chip comprises a memory control chip.

### Claim 14

A semiconductor package comprising:
a base structure comprising a lower surface with a lower connection pad thereon, and an upper surface with an upper connection pad thereon, wherein the upper connection pad is connected to the lower connection pad;
a plurality of first semiconductor chips stacked on the base structure in a vertical direction, wherein the plurality of first semiconductor chips comprises an uppermost first semiconductor chip and a lowermost first semiconductor chip, and wherein each of the plurality of first semiconductor chips comprise a first lower pad, a first upper pad, and a through silicon via (TSV) connecting the first lower pad and the first upper pad;
a second semiconductor chip on the uppermost first semiconductor chip, the second semiconductor chip comprising: a second lower pad directly bonded to the first upper pad of the uppermost first semiconductor chip; and an upper surface comprising a flat region and an edge region having a rounded shape, wherein the edge region is disposed around the flat region; and
an upper dummy chip on the flat region of the second semiconductor chip, the upper dummy chip comprising an area smaller than an area of the second semiconductor chip and a thickness greater than a thickness of the second semiconductor chip,
wherein the first lower pad of the lowermost first semiconductor chip is directly connected to the upper connection pad, and
wherein the first upper pad of each of the plurality of first semiconductor chips, except for the uppermost first semiconductor chip, is directly connected to the first lower pad of another first semiconductor chip, among the plurality of first semiconductor chips, adjacent thereto.

### Claim 15 (depends on 14)

The semiconductor package of claim 14,
wherein the base structure further comprises an upper bonding insulating layer on the upper surface and surrounding a side surface of the upper connection pad,
wherein each of the plurality of first semiconductor chips further comprises:
a first lower insulating layer on a lower surface thereof and surrounding a side surface of the first lower pad; and
a first upper insulating layer on an upper surface thereof and surrounding a side surface of the first upper pad,
wherein the first lower insulating layer of the lowermost first semiconductor chip is directly bonded to the upper bonding insulating layer, and
wherein the first upper insulating layer of each of the plurality of first semiconductor chips, except for the uppermost first semiconductor chip, is directly bonded to the first lower insulating layer of another first semiconductor chip, among the plurality of first semiconductor chips, adjacent thereto.

### Claim 16 (depends on 15)

The semiconductor package of claim 15,
wherein the second semiconductor chip comprises a second lower insulating layer on a lower surface thereof and surrounding a side surface of the second lower pad, and a second upper insulating layer on an upper surface thereof, and
wherein the second lower insulating layer of the second semiconductor chip is directly bonded to the first lower insulating layer of the uppermost first semiconductor chip.

### Claim 17 (depends on 16)

The semiconductor package of claim 16, wherein the upper dummy chip comprises a lower bonding insulating layer to which the second upper insulating layer is directly bonded.

### Claim 18

A semiconductor package comprising:
a base structure comprising a lower surface with a lower connection pad thereon, and an upper surface with an upper connection pad thereon, wherein the upper connection pad is connected to the lower connection pad;
a plurality of first semiconductor chips stacked on the base structure in a vertical direction, wherein the plurality of first semiconductor chips comprises an uppermost first semiconductor chip and a lowermost first semiconductor chip, and wherein each of the plurality of first semiconductor chips comprise a first lower pad, a first upper pad, and a through silicon via connecting the first lower pad to the first upper pad;
a second semiconductor chip disposed on the uppermost first semiconductor chip, the second semiconductor chip comprising a second lower pad directly bonded to the first upper pad of the uppermost first semiconductor chip;
a lower dummy chip disposed on the second semiconductor chip, the lower dummy chip comprising an upper surface, wherein the upper surface comprises a flat region and an edge region having a rounded shape, and wherein the edge region is disposed around the flat region; and
an upper dummy chip disposed on the flat region of the lower dummy chip, the upper dummy chip comprising an area smaller than an area of the lower dummy chip and a thickness greater than a thickness of the second semiconductor chip,
wherein the first lower pad of the lowermost first semiconductor chip is directly bonded to the first upper pad, and
wherein the first upper pad of each the plurality of first semiconductor chips, except for the uppermost first semiconductor chip, is directly bonded to the first lower pad of another first semiconductor chip, among the plurality of first semiconductor chips, adjacent thereto.

### Claim 19 (depends on 18)

The semiconductor package of claim 18,
wherein the base structure further comprises an upper bonding insulating layer disposed on the upper surface and surrounding a side surface of the upper connection pad,
wherein each of the plurality of first semiconductor chips further comprises:
a first lower insulating layer on a lower surface thereof and surrounding a side surface of the first lower pad; and
a first upper insulating layer on an upper surface thereof and surrounding a side surface of the first upper pad,
wherein the first lower insulating layer of the lowermost first semiconductor chip is directly bonded to the upper bonding insulating layer, and
wherein the first upper insulating layer of each the plurality of first semiconductor chips, except for the uppermost first semiconductor chip, is directly bonded to the first lower insulating layer of another first semiconductor chip, among the plurality of first semiconductor chips, adjacent thereto.

### Claim 20 (depends on 19)

The semiconductor package of claim 19,
wherein the second semiconductor chip further comprises:
a second lower insulating layer on a lower surface thereof and surrounding a side surface of the second lower pad, and
a second upper insulating layer on an upper surface thereof, and
wherein the second lower insulating layer is directly bonded to the first lower insulating layer of the uppermost first semiconductor chip.

### Claim at position 21

21-24. (canceled)