# US 2025/0096207 A1 · Package comprising a bridge located between metallization portions > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0096207 A1 - Document ID: US20250096207A1 - Status: Published application - Kind: A1 - Application number: 18/470,344 - Filed: 2023-09-19 - Published: 2025-03-20 - Earliest claimed: 2023-09-19 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Yue LI; Durodami LISK; Ryan LANE; Darko POPOVIC - Web page: https://patentgrep.com/patent/US20250096207A1 ## CPC - H10W 90/00: Package configurations - H10W 70/611: {for connecting multiple chips together} - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/685: comprising multiple insulating layers - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/095: {of vias therein} - H10W 70/635: {Through-vias} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A package comprising a first metallization portion; a first integrated device coupled to the first metallization portion; a bridge coupled to the first metallization portion; an encapsulation layer coupled to the first metallization portion; a second metallization portion coupled to the bridge and the encapsulation layer, such that the first integrated device, the bridge and the encapsulation layer are located between the first metallization portion and the second metallization portion, and a second integrated device coupled to the second metallization portion, wherein the second integrated device and the bridge at least partially vertically overlap. ## Claims ### Claim 1 A package comprising: a first metallization portion comprising: at least one first dielectric layer; and a first plurality of metallization interconnects; a first integrated device coupled to the first metallization portion; a bridge coupled to the first metallization portion; an encapsulation layer coupled to the first metallization portion; a second metallization portion coupled to the bridge and the encapsulation layer, such that the first integrated device, the bridge and the encapsulation layer are located between the first metallization portion and the second metallization portion, wherein the second metallization portion comprises: at least one second dielectric layer; and a second plurality of metallization interconnects; and a second integrated device coupled to the second metallization portion, wherein the second integrated device and the bridge at least partially vertically overlap. ### Claim 2 (depends on 1) The package of claim 1, wherein the bridge comprises: a silicon substrate; and a plurality of bridge interconnects. ### Claim 3 (depends on 1) The package of claim 1, wherein the first integrated device includes a first chiplet and the second integrated device includes a second chiplet. ### Claim 4 (depends on 1) The package of claim 1, wherein the first metallization portion includes a first redistribution portion, wherein the first plurality of metallization interconnects include a first plurality of redistribution interconnects, wherein the second metallization portion includes a second redistribution portion, and wherein the second plurality of metallization interconnects include a second plurality of redistribution interconnects. ### Claim 5 (depends on 1) The package of claim 1, further comprising a plurality of post interconnects located at least partially in the encapsulation layer. ### Claim 6 (depends on 1) The package of claim 1, wherein an electrical path between the first integrated device and the second integrated device includes the first metallization portion, the bridge and the second metallization portion. ### Claim 7 (depends on 1) The package of claim 1, wherein a bridge interconnect of the bridge is coupled to a metallization interconnect from the first metallization portion without any intervening solder interconnect. ### Claim 8 (depends on 1) The package of claim 1, wherein the first integrated device is coupled to a metallization interconnect from the first metallization portion without any intervening solder interconnect. ### Claim 9 (depends on 1) The package of claim 1, further comprising a second encapsulation layer coupled to the second metallization portion and the second integrated device. ### Claim 10 (depends on 9) The package of claim 9, further comprising a plurality of post interconnects located at least partially in the second encapsulation layer. ### Claim 11 (depends on 9) The package of claim 9, further comprising a third metallization portion coupled to the second encapsulation layer. ### Claim 12 (depends on 9) The package of claim 9, further comprising a substrate coupled to the second encapsulation layer. ### Claim 13 (depends on 12) The package of claim 12, wherein the substrate is coupled to a plurality of post interconnects through a plurality of solder interconnects. ### Claim 14 (depends on 12) The package of claim 12, further comprising a third integrated device coupled to the substrate. ### Claim 15 (depends on 1) The package of claim 1, further comprising a plurality of post interconnects located at least partially in the encapsulation layer, wherein the plurality of post interconnects comprise a first pitch, and wherein the bridge comprises a plurality of bridge interconnects comprising a second pitch that is less than the first pitch. ### Claim 16 (depends on 15) The package of claim 15, wherein the second pitch of the plurality of bridge interconnects is about 2-10 times smaller than the first pitch of the plurality of post interconnects. ### Claim 17 (depends on 1) The package of claim 1, wherein the package is implemented in a device that is selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle. ### Claim 18 A package comprising: a first metallization portion comprising: at least one first dielectric layer; and a first plurality of metallization interconnects; a first integrated device coupled to the first metallization portion through at least a first plurality of solder interconnects; a bridge coupled to the first metallization portion through at least a second plurality of solder interconnects; an encapsulation layer coupled to the first metallization portion; a second metallization portion coupled to the bridge and the encapsulation layer, such that the first integrated device, the bridge and the encapsulation layer are located between the first metallization portion and the second metallization portion, wherein the second metallization portion comprises: at least one second dielectric layer; and a second plurality of metallization interconnects; and a second integrated device coupled to the second metallization portion through at least a third plurality of solder interconnects, wherein the second integrated device and the bridge at least partially vertically overlap. ### Claim 19 (depends on 18) The package of claim 18, wherein the bridge comprises: a silicon substrate; and a plurality of bridge interconnects. ### Claim 20 (depends on 18) The package of claim 18, wherein the first integrated device includes a first chiplet and the second integrated device includes a second chiplet. ### Claim 21 (depends on 18) The package of claim 18, wherein the first metallization portion includes a first redistribution portion, wherein the first plurality of metallization interconnects include a first plurality of redistribution interconnects, wherein the second metallization portion includes a second redistribution portion, and wherein the second plurality of metallization interconnects include a second plurality of redistribution interconnects. ### Claim 22 (depends on 18) The package of claim 18, further comprising a plurality of post interconnects located at least partially in the encapsulation layer. ### Claim 23 (depends on 18) The package of claim 18, wherein an electrical path between the first integrated device and the second integrated device includes a solder interconnect from the first plurality of solder interconnects, the first metallization portion, a solder interconnect from the second plurality of solder interconnects, the bridge, the second metallization portion and a solder interconnect from the third plurality of solder interconnects. ### Claim 24 (depends on 18) The package of claim 18, further comprising a second encapsulation layer coupled to the second metallization portion and the second integrated device. ### Claim 25 (depends on 24) The package of claim 24, further comprising a plurality of post interconnects located at least partially in the second encapsulation layer. ### Claim 26 (depends on 24) The package of claim 24, further comprising a third metallization portion coupled to the second encapsulation layer. ### Claim 27 (depends on 24) The package of claim 24, further comprising a substrate coupled to the second encapsulation layer. ### Claim 28 (depends on 27) The package of claim 27, further comprising a plurality of post interconnects located in the second encapsulation layer, wherein the substrate is coupled to the plurality of post interconnects through a fourth plurality of solder interconnects. ### Claim 29 (depends on 28) The package of claim 28, further comprising a third integrated device coupled to the substrate. ### Claim 30 (depends on 18) The package of claim 18, further comprising a plurality of post interconnects located at least partially in the encapsulation layer, wherein the plurality of post interconnects comprises a first pitch, and wherein the bridge comprises a plurality of bridge interconnects comprising a second pitch that is less than the first pitch. ### Claim 31 (depends on 30) The package of claim 30, wherein the second pitch of the plurality of bridge interconnects is about 2-10 times smaller than the first pitch of the plurality of post interconnects. ### Claim 32 (depends on 18) The package of claim 18, wherein the package is implemented in a device that is selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle.