# US 2025/0096201 A1 · Semiconductor package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0096201 A1 - Document ID: US20250096201A1 - Status: Published application - Kind: A1 - Application number: 18/599,390 - Filed: 2024-03-08 - Published: 2025-03-20 - Earliest claimed: 2023-09-14 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Gyujin CHOI; Dahee KIM; Hwan Pil PARK; Taehoon LEE; Younjeong CHOE - Web page: https://patentgrep.com/patent/US20250096201A1 ## CPC - H10W 90/00: Package configurations - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/0198: {batch processes} - H10W 72/07254: {changes in dispositions} - H10W 72/07354: {changes in dispositions} - H10W 72/247: {Dispositions of multiple bumps} - H10W 72/347: {Dispositions of multiple die-attach connectors} - H10W 72/926: {Multiple bond pads having different sizes} - H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/944: {Dispositions of multiple bond pads} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/732: {between stacked chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract The present disclosure relates to a semiconductor package which includes a wiring structure including insulating layers, wiring layers, and vias, a chip stack structure including a plurality of semiconductor chips and being oblique on the wiring structure such that the plurality of semiconductor chips are inclined with respect to the wiring structure, and a sealing material encapsulating the chip stack structure, wherein each of the plurality of semiconductor chips includes connection pads on one surface of the semiconductor chip, and the plurality of semiconductor chips are being offset with each other such that the connection pads are exposed, and each of the connection pads of each of the plurality of semiconductor chips is in contact with one of the vias and connected to the wiring layers. ## Claims ### Claim 1 A semiconductor package comprising: a wiring structure including insulating layers, wiring layers, and vias; a chip stack structure including a plurality of semiconductor chips, the chip stack structure being oblique on the wiring structure such that the plurality of semiconductor chips is inclined with respect to the wiring structure; and a sealing material encapsulating the chip stack structure, wherein each of the plurality of semiconductor chips includes connection pads on one surface thereof, the plurality of semiconductor chips being offset with each other such that the connection pads are exposed, and each of the connection pads of each of the plurality of semiconductor chips is in contact with a corresponding one of the vias and connected to the wiring layers. ### Claim 2 (depends on 1) The semiconductor package of claim 1, further comprising: a support member on an uppermost semiconductor chip of the plurality of semiconductor chips and exposed to one surface of the sealing material. ### Claim 3 (depends on 1) The semiconductor package of claim 1, further comprising: a support member on the wiring structure and in contact with a lowermost semiconductor chip of the plurality of semiconductor chips. ### Claim 4 (depends on 1) The semiconductor package of claim 1, further comprising: an electronic device on an uppermost semiconductor chip of the plurality of semiconductor chips and exposed to one surface of the sealing material, where the electronic device includes one or more conductive pads, each of the one or more conductive pads being in contact with a corresponding one of the vias and connected to the wiring layers. ### Claim 5 (depends on 1) The semiconductor package of claim 1, further comprising: an electronic device on the wiring structure and in contact with a lowermost semiconductor chip of the plurality of semiconductor chips, where the electronic device includes one or more conductive pads, each of the one or more conductive pads being in contact with a corresponding one of the vias and connected to the wiring layers. ### Claim 6 (depends on 1) The semiconductor package of claim 1, wherein the chip stack structure further includes bonding members between the plurality of semiconductor chips. ### Claim 7 (depends on 1) The semiconductor package of claim 1, wherein each of the plurality of semiconductor chips further includes a protrusion on the one surface thereof, the protrusion being spaced apart from a corresponding one of the connection pads in a direction in which the plurality of semiconductor chips are offset with each other, and each of the plurality of semiconductor chips is on the one surface of another semiconductor chip of the plurality of semiconductor chips, to be adjacent to the protrusion of the another semiconductor chip. ### Claim 8 (depends on 7) The semiconductor package of claim 7, wherein the protrusion is a conductive pad and includes a same material as that the connection pad. ### Claim 9 (depends on 7) The semiconductor package of claim 7, wherein each of the plurality of semiconductor chips further includes a passivation layer on the one surface thereof and exposes the connection pad, and the protrusion is an insulating layer on the passivation layer and includes a same material as the passivation layer. ### Claim 10 (depends on 1) The semiconductor package of claim 1, wherein each of the plurality of semiconductor chips further includes through-vias, and the plurality of semiconductor chips are electrically connected to one another through the through-vias. ### Claim 11 (depends on 10) The semiconductor package of claim 10, wherein each of the plurality of semiconductor chips further includes, conductive pads on the one surface thereof and connected to the through-vias, and via pads on another surface thereof and connected to the through-vias, the another surface being opposite to the one surface, and the chip stack structure further includes conductive bumps between the plurality of semiconductor chips and connecting the conductive pads and the via pads. ### Claim 12 (depends on 10) The semiconductor package of claim 10, wherein each of the plurality of semiconductor chips further includes, conductive pads on the one surface thereof and connected to the through-vias, and via pads on another surface thereof and connected to the through-vias, and the conductive pads of each of the plurality of semiconductor chips are in contact with the via pads of another semiconductor chip adjacent thereto, from among the plurality of semiconductor chips. ### Claim 13 (depends on 1) The semiconductor package of claim 1, wherein a width of each of the vias decreases in a direction from the wiring layers toward the connection pads. ### Claim 14 (depends on 1) The semiconductor package of claim 1, wherein the connection pads include a plurality of connection pads, the plurality of connection pads being at intervals on one end portion of each of the plurality of semiconductor chips, and the plurality of semiconductor chips are offset with each other in a direction from the one end portion toward another end portion, the one end portion and the another end portion being opposite end portions of each of the plurality of semiconductor chips. ### Claim 15 A semiconductor package comprising: a wiring structure; a first chip stack structure on the wiring structure and including a plurality of first semiconductor chips, the plurality of first semiconductor chips being offset with each other, the first chip stack structure being oblique along a first direction such that the plurality of first semiconductor chips are inclined with respect to the wiring structure; a first sealing material encapsulating the first chip stack structure; a second chip stack structure on the first chip stack structure and including a plurality of second semiconductor chips being offset with each other, and the second chip stack structure being oblique along a second direction forming an angle with the first direction; and a second sealing material encapsulating the second chip stack structure, wherein each of the plurality of first semiconductor chips includes, first connection pads on one end portion thereof and electrically connected to the wiring structure, and second connection pads on another end portion thereof, the one end portion and the another end portion of each of the plurality of first semiconductor chips being opposite to each other, and each of the plurality of second semiconductor chips includes third connection pads on one end portion thereof and electrically connected to the second connection pad. ### Claim 16 (depends on 15) The semiconductor package of claim 15, wherein the second connection pads and the third connection pads are in contact with each other. ### Claim 17 (depends on 15) The semiconductor package of claim 15, further comprising: a third chip stack structure including a plurality of third semiconductor chips being offset with each other, the third chip stack structure being on the second chip stack structure and being oblique along the first direction; and a third sealing material encapsulating the third chip stack structure, wherein each of the plurality of second semiconductor chips further includes fourth connection pads on another end portion thereof, the one end portion and the another end portion of each of the plurality of second semiconductor chips being opposite to each other, and each of the plurality of third semiconductor chips includes fifth connection pads being on one end portion thereof and electrically connected to the fourth connection pad. ### Claim 18 (depends on 17) The semiconductor package of claim 17, further comprising: at least one of a first support member on the wiring structure and being in contact with a lowermost first semiconductor chip of the plurality of first semiconductor chips, a second support member on an uppermost second semiconductor chip of the plurality of second semiconductor chips and exposed to one surface of the second sealing material, or a third support member on the second sealing material and in contact with a lowermost third semiconductor chip of the plurality of third semiconductor chips. ### Claim 19 A semiconductor package comprising: a first semiconductor package; and a second semiconductor package on the first semiconductor package, wherein the first semiconductor package includes, a wiring structure, a chip stack structure including a plurality of first semiconductor chips being offset with each other, the chip stack structure being oblique on the wiring structure such that the plurality of first semiconductor chips are inclined with respect to the wiring structure, and a sealing material encapsulating the chip stack structure, each of the plurality of first semiconductor chips includes, first connection pads being on one end portion thereof and electrically connected to the wiring structure, and second connection pads being on another end portion of first semiconductor chip and electrically connected to the second semiconductor package, and the second semiconductor package includes a plurality of second semiconductor chips. ### Claim 20 (depends on 19) The semiconductor package of claim 19, wherein the second connection pads are exposed to one surface of the sealing material.