# US 2025/0096199 A1 · Semiconductor package structures and methods of forming same

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- Number: US 2025/0096199 A1
- Document ID: US20250096199A1
- Status: Published application
- Kind: A1
- Application number: 18/412,779
- Filed: 2024-01-15
- Published: 2025-03-20
- Earliest claimed: 2023-09-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yen-Liang Lin; Tzuan-Horng Liu; An-Jhih Su
- Web page: https://patentgrep.com/patent/US20250096199A1

## CPC

- H10W 90/00: Package configurations
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/42: Vias, e.g. via plugs
- H10W 74/01: Manufacture or treatment
- H10W 74/014: {using batch processing}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10P 72/7416: {used during dicing or grinding}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto}
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/072: {of bump connectors}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An embodiment is a method including forming a first die, the forming including forming through vias in a first substrate. The method also includes forming a first redistribution structure over the through vias and the first substrate, the first redistribution structure being electrically coupled to the through vias. The method also includes forming a first set of die connectors over and electrically coupled to the first redistribution structure, the first set of die connectors being on a first side of the first substrate. The method also includes bonding the first die to a second die. The method also includes encapsulating the first die with a first encapsulant. The method also includes forming a second set of die connectors over and electrically coupled to the first set of die connectors, the first and second sets of die connectors forming stacked die connectors.

## Claims

### Claim 1

A method comprising:
forming a first die, the forming comprising:
forming through vias in a first substrate;
forming a first redistribution structure over the through vias and the first substrate, the first redistribution structure being electrically coupled to the through vias;
forming a first set of die connectors over and electrically coupled to the first redistribution structure, the first set of die connectors being on a first side of the first substrate;
thinning a second side of the first substrate, the thinning exposing the through vias;
bonding the first die to a second die;
encapsulating the first die with a first encapsulant; and
forming a second set of die connectors over and electrically coupled to the first set of die connectors, the first and second sets of die connectors forming stacked die connectors.

### Claim 2 (depends on 1)

The method of claim 1 further comprising:
forming a first dielectric layer on the first set of die connectors and the first redistribution structure, the first dielectric layer having sidewalls coterminous with sidewalls of the first redistribution structure, the first set of die connectors being in the first dielectric layer.

### Claim 3 (depends on 2)

The method of claim 2 further comprising:
forming a second dielectric layer on the first set of die connectors, the first dielectric layer, and the first encapsulant, the second set of die connectors being in the second dielectric layer.

### Claim 4 (depends on 3)

The method of claim 3, wherein the second dielectric layer has sidewalls coterminous with sidewalls of the first encapsulant.

### Claim 5 (depends on 3)

The method of claim 3, wherein the first and second dielectric layers are polymer layers.

### Claim 6 (depends on 5)

The method of claim 5, wherein the first and second dielectric layers comprise different materials.

### Claim 7 (depends on 3)

The method of claim 3, wherein the first encapsulant contacts the sidewalls of the first dielectric layer and the first redistribution structure.

### Claim 8 (depends on 1)

The method of claim 1, wherein the first set of die connectors have different widths than the second set of die connectors.

### Claim 9 (depends on 1)

The method of claim 1, wherein the first set of die connectors are wider than the second set of die connectors.

### Claim 10 (depends on 1)

The method of claim 1, further comprising:
forming conductive features over a carrier substrate;
attaching the bonded first and second dies to the carrier substrate adjacent the conductive features;
encapsulating the bonded first and second dies and the conductive features in a second encapsulant; and
forming a second redistribution structure over the bonded first and second dies, the conductive features, and the second encapsulant, the second redistribution structure being electrically coupled to the second set of die connectors and the conductive features.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
forming conductive connectors over and electrically coupled to the second redistribution structure;
removing the carrier substrate; and
bonding the conductive connectors to a package substrate.

### Claim 12

A method comprising:
encapsulating a first integrated circuit die in a first encapsulant, the first integrated circuit die comprising a first substrate and active devices;
forming a first redistribution structure over the first integrated circuit die and the first encapsulant;
forming a second integrated circuit die comprising a second substrate and active devices, forming the second integrated circuit die comprising:
forming through vias in the second substrate;
forming a second redistribution structure over the through vias and the second substrate, the second redistribution structure being electrically coupled to the through vias;
forming a first set of conductive vias over and electrically coupled to the second redistribution structure, the first set of conductive vias being on a first side of the second substrate;
thinning a second side of the second substrate, the thinning exposing the through vias;
bonding the first integrated circuit die to the second integrated circuit die;
encapsulating the second integrated circuit die with a second encapsulant; and
forming a second set of conductive vias over and electrically coupled to the first set of conductive vias, the first and second sets of conductive vias forming stacked conductive vias.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
forming a first polymer layer on the first set of conductive vias and the second redistribution structure, the first polymer layer having sidewalls coterminous with sidewalls of the second redistribution structure, the first set of conductive vias being in the first polymer layer.

### Claim 14 (depends on 13)

The method of claim 13 further comprising:
forming a second polymer layer on the first set of conductive vias, the first polymer layer, and the second encapsulant, the second set of conductive vias being in the second polymer layer.

### Claim 15 (depends on 14)

The method of claim 14, wherein the second polymer layer has sidewalls coterminous with sidewalls of the second encapsulant.

### Claim 16 (depends on 12)

The method of claim 12, further comprising:
forming conductive features over a carrier substrate;
attaching the bonded first and second integrated circuit dies to the carrier substrate adjacent the conductive features;
encapsulating the bonded first and second integrated circuit dies and the conductive features in a third encapsulant, the third encapsulant contacting the first and second encapsulants; and
forming a third redistribution structure over the second integrated circuit die, the conductive features, and the third encapsulant, the third redistribution structure being electrically coupled to the second set of conductive vias and the conductive features.

### Claim 17

A structure comprising:
a first integrated circuit die bonded to a second integrated circuit die, the first integrated circuit die being in a first encapsulant, the first integrated circuit die comprising:
a first substrate;
active devices;
through vias in the first substrate;
a first redistribution structure over the through vias and the first substrate, the first redistribution structure being electrically coupled to the through vias;
a first set of conductive vias over and electrically coupled to the first redistribution structure, the first set of conductive vias being on a first side of the first substrate; and
a second set of conductive vias over and electrically coupled to the first set of conductive vias, the first and second sets of conductive vias forming stacked conductive vias.

### Claim 18 (depends on 17)

The structure of claim 17, further comprising:
a second encapsulant on the second integrated circuit die, the second integrated circuit die comprising a second substrate and active devices; and
a second redistribution structure over the second integrated circuit die and the first encapsulant.

### Claim 19 (depends on 18)

The structure of claim 18, further comprising:
a first polymer layer on the first set of conductive vias and the second redistribution structure, the first polymer layer having sidewalls coterminous with sidewalls of the second redistribution structure, the first set of conductive vias being in the first polymer layer; and
a second polymer layer on the first set of conductive vias, the first polymer layer, and the second encapsulant, the second set of conductive vias being in the second polymer layer, the second polymer layer has sidewalls coterminous with sidewalls of the second encapsulant.

### Claim 20 (depends on 17)

The structure of claim 17, wherein the first set of conductive vias have different widths than the second set of conductive vias.