# US 2025/0096178 A1 · Microelectronic package with solder array thermal interface material (sa-tim)

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- Number: US 2025/0096178 A1
- Document ID: US20250096178A1
- Status: Published application
- Kind: A1
- Application number: 18/969,889
- Filed: 2024-12-05
- Published: 2025-03-20
- Earliest claimed: 2019-06-25
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Debendra Mallik; Sergio Antonio Chan Arguedas; Jimin Yao; Chandra Mohan Jha
- Web page: https://patentgrep.com/patent/US20250096178A1

## CPC

- H10W 40/70: Fillings or auxiliary members in containers or in encapsulations for thermal protection or control
- H10W 76/40: Fillings or auxiliary members in containers, e.g. centering rings (fillings or auxiliary members for thermal protection or control in containers or encapsulations H10W40/70)
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 40/77: Auxiliary members characterised by their shape
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/013: {of die-attach connectors}
- H10W 72/01323: {in liquid form, e.g. by dispensing droplets or by screen printing}
- H10W 72/01336: {in solid form, e.g. by using a powder or by laminating a foil}
- H10W 72/019: {of bond pads}
- H10W 72/072: {of bump connectors}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/07253: {changes in shapes}
- H10W 72/07254: {changes in dispositions}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07338: {hardening the adhesive by curing, e.g. thermosetting}
- H10W 72/07352: {changes in structures or sizes}
- H10W 72/07353: {changes in shapes}
- H10W 72/07354: {changes in dispositions}
- H10W 72/07355: {changes in materials}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/232: {Plan-view shape, i.e. in top view}
- H10W 72/237: {Multiple bump connectors having different shapes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/265: {Providing thermal transfer, e.g. thermal bumps}
- H10W 72/267: {Multiple bump connectors having different functions}
- H10W 72/321: {Structures or relative sizes of die-attach connectors}
- H10W 72/334: {Cross-sectional shape, i.e. in side view}
- H10W 72/347: {Dispositions of multiple die-attach connectors}
- H10W 72/3528: {Intermetallic compounds}
- H10W 72/354: {comprising polymers}
- H10W 72/357: {Multiple die-attach connectors having different materials}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 76/60: Seals
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A plurality of solder thermal interface material (STIM) thermal interconnects may be coupled with the die and an integrated heat spreader (IHS) may be coupled with the plurality of STIM thermal interconnects. A thermal underfill material may be positioned between the IHS and the die such that the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects. Other embodiments may be described or claimed.

## Claims

### Claim 1

A microelectronic package, comprising:
a package substrate;
a die coupled with the package substrate at a first face of the die;
a plurality of solder thermal interface material (STIM) interconnects coupled with the die at a second face of the die, wherein the second face is opposite the first face;
a heat spreader coupled with the plurality of STIM interconnects;
an underfill material between the heat spreader and the die, wherein the underfill material at least partially surrounds the plurality of STIM interconnects; and
a solder resist layer at least partially surrounding a STIM interconnect of the plurality of STIM interconnects.

### Claim 2 (depends on 1)

The microelectronic package of claim 1, further comprising a patterning layer positioned between a STIM interconnect of the plurality of STIM interconnects and the heat spreader.

### Claim 3 (depends on 1)

The microelectronic package of claim 1, wherein the solder resist layer is coupled to the second face of the die.

### Claim 4 (depends on 1)

The microelectronic package of claim 1, wherein the solder resist layer is coupled to the heat spreader.

### Claim 5 (depends on 1)

The microelectronic package of claim 1, wherein one STIM interconnect of the plurality of STIM interconnects has a different size or shape than another STIM interconnect of the plurality of STIM interconnects.

### Claim 6 (depends on 1)

The microelectronic package of claim 1, wherein the plurality of STIM interconnects are coupled with the second face of the die in a two-dimensional array pattern.

### Claim 7 (depends on 1)

The microelectronic package of claim 1, wherein a distance between the second face of the die and the heat spreader is less than 150 micrometers.

### Claim 8 (depends on 1)

The microelectronic package of claim 1, wherein the underfill material is a thermal underfill material.

### Claim 9

A microelectronic package, comprising:
a die coupled with a package substrate;
solder thermal interface material (STIM) interconnects coupled with the die, wherein the STIM interconnects are at least partially surrounded by an underfill material;
a heat spreader coupled with the STIM interconnects, wherein the die is between the heat spreader and the package substrate; and
a spacer physically coupled with the heat spreader and the package substrate, wherein the spacer includes one or more of steel, copper, aluminum, or polymer.

### Claim 10 (depends on 9)

The microelectronic package of claim 9, wherein the spacer is to stiffen an outer periphery of the heat spreader.

### Claim 11 (depends on 9)

The microelectronic package of claim 9, wherein the spacer is to provide a mechanical load bearing spacing between the heat spreader and the package substrate.

### Claim 12 (depends on 9)

The microelectronic package of claim 9, wherein the spacer is a first spacer and wherein the microelectronic package further comprises a second spacer adjacent to the first spacer, and wherein the second spacer is physically coupled with the heat spreader and the package substrate.

### Claim 13 (depends on 9)

The microelectronic package of claim 9, wherein the spacer is a solder ball.

### Claim 14 (depends on 9)

The microelectronic package of claim 9, wherein the STIM interconnects have a height of less than 50 micrometers.

### Claim 15

A microelectronic package, comprising:
a die coupled with a package substrate;
solder thermal interface material (STIM) interconnects coupled with the die, wherein the STIM interconnects are at least partially surrounded by an underfill material;
a heat spreader coupled with the STIM interconnects, wherein the die is between the heat spreader and the package substrate;
a first spacer physically coupled with the heat spreader and the package substrate; and
a second spacer physically coupled with the heat spreader and the package substrate.

### Claim 16 (depends on 15)

The microelectronic package of claim 15, wherein the second spacer is adjacent to the first spacer.

### Claim 17 (depends on 15)

The microelectronic package of claim 15, wherein the first spacer includes one or more of steel, copper, aluminum, or polymer.

### Claim 18 (depends on 15)

The microelectronic package of claim 15, wherein the first spacer is a solder ball.

### Claim 19 (depends on 15)

The microelectronic package of claim 15, wherein the STIM interconnects are coupled with the die in a two-dimensional array pattern.

### Claim 20 (depends on 15)

The microelectronic package of claim 15, wherein a distance between the die and the heat spreader is less than 150 micrometers.