# US 2025/0096162 A1 · Semiconductor structure and manufacturing method therefor

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- Number: US 2025/0096162 A1
- Document ID: US20250096162A1
- Status: Published application
- Kind: A1
- Application number: 18/963,499
- Filed: 2024-11-28
- Published: 2025-03-20
- Earliest claimed: 2023-07-14
- Assignees: CXMT Corporation
- Applicants: Cxmt Corporation
- Inventors: You FU; Shuangshuang WU; TZUNG-HAN LEE; CHIH-CHENG LIU; Xiaolong CHEN
- Web page: https://patentgrep.com/patent/US20250096162A1

## CPC

- H10W 44/601: {Capacitive arrangements (H10W44/20 takes precedence)}
- H10D 84/00: Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10W 10/011: {of isolation regions comprising dielectric materials}
- H10W 10/10: Isolation regions comprising dielectric materials
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 44/00: Electrical arrangements for controlling or matching impedance
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor structure and a manufacturing method therefor are disclosed. The semiconductor structure includes an interposer, where the interposer includes a deep trench capacitor array and an isolation structure. The deep trench capacitor array includes multiple deep trench capacitors, and the isolation structure at least partially surrounds a deep trench capacitor on the outmost edge side of the deep trench capacitor array.

## Claims

### Claim 1

A semiconductor structure, comprising:
an interposer comprising a deep trench capacitor array and an isolation structure, wherein
the deep trench capacitor array comprises a plurality of deep trench capacitors, and the isolation structure at least partially surrounding a deep trench capacitor on an outmost edge side of the deep trench capacitor array.

### Claim 2 (depends on 1)

The semiconductor structure according to claim 1, wherein
each of the deep trench capacitors comprises a first electrode layer, a capacitor dielectric layer, a second electrode layer, and a conductive layer, wherein
the first electrode layer covers an inner surface of a deep trench in the interposer and extends to an upper surface of the interposer, the capacitor dielectric layer covers the first electrode layer, the second electrode layer covers the capacitor dielectric layer, and the conductive layer covers the second electrode layer.

### Claim 3 (depends on 2)

The semiconductor structure according to claim 2, wherein the isolation structure comprises a first isolation structure, an isolation trench is disposed in the interposer, and the first isolation structure is located in the isolation trench; and for the deep trench capacitor array,
on a side away from the first isolation structure, ends of the first electrode layer, the capacitor dielectric layer, the second electrode layer, and the conductive layer that are of the deep trench capacitor on the outmost edge side and that are located on the upper surface of the interposer completely overlap; and
on a side close to the first isolation structure, the deep trench capacitor on the outmost edge side exposes a part of the first electrode layer, ends of the capacitor dielectric layer, the second electrode layer, and the conductive layer that are of the deep trench capacitor on the outmost edge side and that are located on the upper surface of the interposer completely overlap, and a remaining part of the first electrode layer located on the upper surface of the interposer is covered by the capacitor dielectric layer.

### Claim 4 (depends on 3)

The semiconductor structure according to claim 3, wherein
the semiconductor structure further comprises a dielectric material layer, and the dielectric material layer covers the conductive layer located in the deep trench and completely fills the deep trench.

### Claim 5 (depends on 3)

The semiconductor structure according to claim 3, wherein
the semiconductor structure further comprises an insulating layer, and the insulating layer is located between the deep trench capacitor array and the interposer and is exposed on the interposer on a side that is of the deep trench capacitor on the outmost edge side and that is away from the first isolation structure.

### Claim 6 (depends on 5)

The semiconductor structure according to claim 5, wherein
the isolation structure further comprises a second isolation structure, and the second isolation structure covers the deep trench capacitor array, the first isolation structure, and the insulating layer being exposed.

### Claim 7 (depends on 3)

The semiconductor structure according to claim 3, wherein
on a cross-section perpendicular to a first direction, a cross-sectional shape of the first isolation structure is a rectangle, a trapezoid, an inverted trapezoid, or an oval, and the first direction is perpendicular to a vertical direction.

### Claim 8 (depends on 3)

The semiconductor structure according to claim 3, wherein
an aspect ratio of the isolation trench is 2 to 10.

### Claim 9 (depends on 1)

The semiconductor structure according to claim 1, wherein
projections of the plurality of deep trench capacitors on an upper surface of the interposer in the vertical direction are arranged in a shape of a regular hexagon.

### Claim 10

A manufacturing method for a semiconductor structure, comprising:
providing an interposer;
forming an initial deep trench capacitor array structure in the interposer, the initial deep trench capacitor array structure comprising a plurality of initial deep trench capacitor structures;
performing a first etching on the initial deep trench capacitor array structure to expose a first electrode layer on a periphery of an initial deep trench capacitor structure on an outmost edge side of the initial deep trench capacitor array structure, to form an intermediate deep trench capacitor array structure;
performing a second etching on the intermediate deep trench capacitor array structure to etch a side that is of the first electrode layer being exposed and that is away from the initial deep trench capacitor structure on the outmost edge side to form an isolation trench, and cut off adjacent capacitor cells in the intermediate deep trench capacitor array structure to form a deep trench capacitor array; and
filling an isolation material in the isolation trench to form an isolation structure, the isolation structure at least partially surrounding a deep trench capacitor on an outmost edge side of the deep trench capacitor array.

### Claim 11 (depends on 10)

The manufacturing method for a semiconductor structure according to claim 10, wherein the forming an initial deep trench capacitor array structure in the interposer comprises:
forming a deep trench array in the interposer, the deep trench array comprising a plurality of deep trenches;
depositing an insulating material on an upper surface of the interposer and in each of the deep trenches to form an insulating layer, the insulating layer covering an inner surface of the deep trench and extends to the upper surface of the interposer; and
sequentially depositing the first electrode layer, a capacitor dielectric layer, a second electrode layer, and a conductive layer on the insulating layer to form the initial deep trench capacitor array structure, the first electrode layer covering the insulating layer, the capacitor dielectric layer covering the first electrode layer, the second electrode layer covering the capacitor dielectric layer, and the conductive layer covering the second electrode layer.

### Claim 12 (depends on 11)

The manufacturing method for a semiconductor structure according to claim 11, after the forming an initial deep trench capacitor array structure in the interposer, comprising:
depositing a dielectric material on the conductive layer, the dielectric material covering the conductive layer in the deep trench and completely filling the deep trench to form a dielectric material layer.

### Claim 13 (depends on 11)

The manufacturing method for a semiconductor structure according to claim 11, wherein the performing a first etching on the initial deep trench capacitor array structure comprises:
forming a patterned first mask layer on the initial deep trench capacitor array structure; and
performing the first etching on the initial deep trench capacitor array structure based on the patterned first mask layer to form a first trench on the periphery of the initial deep trench capacitor structure on the outmost edge side of the initial deep trench capacitor array structure, the first trench exposing the first electrode layer, and a remaining initial deep trench capacitor array structure serving as the intermediate deep trench capacitor array structure.

### Claim 14 (depends on 13)

The manufacturing method for a semiconductor structure according to claim 13, wherein the performing a second etching on the intermediate deep trench capacitor array structure comprises:
forming a patterned second mask layer on the intermediate deep trench capacitor array structure; and
performing the second etching on the intermediate deep trench capacitor array structure based on the patterned second mask layer to form the isolation trench on a side that is of the first trench and that is away from the initial deep trench capacitor structure on the outmost edge side, and cut off adjacent capacitor cells in the intermediate deep trench capacitor array structure to expose a part of the insulating layer, the isolation trench extending into the interposer, and a remaining intermediate deep trench capacitor array structure serving as the deep trench capacitor array.

### Claim 15 (depends on 14)

The manufacturing method for a semiconductor structure according to claim 14, wherein the filling an isolation material in the isolation trench to form an isolation structure comprises:
depositing the isolation material on the interposer on which the deep trench capacitor array is formed, a part of the isolation material completely filling the isolation trench to form a first isolation structure, a part of the isolation material covering the deep trench capacitor array, the first isolation structure, and the insulating layer being exposed to form a second isolation structure, and the first isolation structure and the second isolation structure forming the isolation structure.