# US 2025/0096155 A1 · Semiconductor device and method for forming the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0096155 A1 - Document ID: US20250096155A1 - Status: Published application - Kind: A1 - Application number: 18/469,410 - Filed: 2023-09-18 - Published: 2025-03-20 - Earliest claimed: 2023-09-18 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Wen-Chieh LO; Wei-Tse HSU; Ya-Ching TSENG; Yung-Shih CHENG - Web page: https://patentgrep.com/patent/US20250096155A1 ## CPC - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10P 95/062: {involving a dielectric removal step} - H10W 20/01: {Manufacture or treatment} - H10W 20/023: {the interconnections being through-semiconductor vias} - H10W 20/43: Layouts of interconnections - H10W 74/01: Manufacture or treatment - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A method for forming a semiconductor device is provided. The method includes forming a device layer over a device substrate and forming a front-side interconnect structure over the device layer. The method also includes forming a bevel oxide over an edge portion of the device substrate, an edge portion of the device layer, and an edge portion of the front-side interconnect structure. The method further includes forming an oxide layer over the device layer, the front-side interconnect structure, and the bevel oxide, polishing the bevel oxide and the oxide layer until a top surface of the bevel oxide is substantially level with a top surface of the oxide layer, and attaching a carrier substrate to the bevel oxide and the oxide layer. ## Claims ### Claim 1 A method for forming a semiconductor device, comprising: forming a device layer over a device substrate; forming a front-side interconnect structure over the device layer; forming a bevel oxide over an edge portion of the device substrate, an edge portion of the device layer, and an edge portion of the front-side interconnect structure; forming an oxide layer over the device layer, the front-side interconnect structure, and the bevel oxide; polishing the bevel oxide and the oxide layer until a top surface of the bevel oxide is substantially level with a top surface of the oxide layer; and attaching a carrier substrate to the bevel oxide and the oxide layer. ### Claim 2 (depends on 1) The method as claimed in claim 1, further comprising flipping over the device substrate and thinning the device substrate. ### Claim 3 (depends on 2) The method as claimed in claim 2, further comprising forming a back-side interconnect structure over the device layer, wherein the back-side interconnect structure comprises a plurality of back-side vias, a plurality of back-side through vias, and a plurality of back-side metal pads. ### Claim 4 (depends on 1) The method as claimed in claim 1, wherein the bevel oxide and the oxide layer are polished by performing a chemical mechanical polishing process, and a polishing rate of the oxide layer is different from a polishing rate of the bevel oxide during the chemical mechanical polishing process. ### Claim 5 (depends on 1) The method as claimed in claim 1, wherein the bevel oxide has a bevel oxide recessed portion filled with the oxide layer before the bevel oxide and the oxide layer are polished. ### Claim 6 (depends on 5) The method as claimed in claim 5, wherein the oxide layer has an oxide layer recessed portion vertically overlapping the bevel oxide recessed portion before the bevel oxide and the oxide layer are polished. ### Claim 7 (depends on 5) The method as claimed in claim 5, wherein the oxide layer has an oxide layer extending portion extending into the bevel oxide recessed portion, and the oxide layer extending portion is exposed after the bevel oxide and the oxide layer are polished. ### Claim 8 (depends on 1) The method as claimed in claim 1, further comprising trimming the bevel oxide, the front-side interconnect structure, and the device substrate before the carrier substrate is attached to the bevel oxide and the oxide layer. ### Claim 9 (depends on 8) The method as claimed in claim 8, wherein a width of a top surface of the device substrate is less than a width of a bottom surface of the device substrate after the bevel oxide, the front-side interconnect structure, and the device substrate are trimmed. ### Claim 10 (depends on 1) The method as claimed in claim 1, wherein a width of a top surface of the front-side interconnect structure is different from a width of a bottom surface of the front-side interconnect structure. ### Claim 11 A method for forming a semiconductor device, comprising: forming transistors over a front-side surface of a device substrate; forming a first interconnect structure over the transistors; forming an oxide layer and a bevel oxide over the device substrate; partially removing the oxide layer and the bevel oxide until a top surface of the oxide layer is substantially level with a top surface of the bevel oxide; attaching a carrier substrate to the oxide layer and the bevel oxide; and polishing a back-side surface of the device substrate, wherein the device substrate has a device recessed portion formed on the front-side surface. ### Claim 12 (depends on 11) The method as claimed in claim 11, wherein the oxide layer has an oxide layer recessed portion, the bevel oxide has a bevel oxide recessed portion, and the device recessed portion, the oxide layer recessed portion, and the bevel oxide recessed portion at least partially overlap each other vertically. ### Claim 13 (depends on 12) The method as claimed in claim 12, wherein the bevel oxide recessed portion is between the oxide layer recessed portion and the device recessed portion. ### Claim 14 (depends on 12) The method as claimed in claim 12, wherein the oxide layer recessed portion is between the bevel oxide recessed portion and the device recessed portion. ### Claim 15 (depends on 11) The method as claimed in claim 11, further comprising forming a seal between the carrier substrate and the bevel oxide. ### Claim 16 A semiconductor device, comprising: a device layer; a front-side interconnect structure over a front-side surface of the device layer; a back-side interconnect structure over a back-side surface of the device layer; an oxide layer covering a central region of the front-side interconnect structure; and a bevel oxide covering a bevel region of the front-side interconnect structure, wherein the oxide layer and the bevel oxide are made of different dielectric materials. ### Claim 17 (depends on 16) The semiconductor device as claimed in claim 16, wherein a width of the bevel oxide is less than a width of the oxide layer. ### Claim 18 (depends on 16) The semiconductor device as claimed in claim 16, wherein a maximum thickness of the bevel oxide is greater than a maximum thickness of the oxide layer. ### Claim 19 (depends on 18) The semiconductor device as claimed in claim 18, wherein a minimum thickness of the bevel oxide is substantially the same as the maximum thickness of the oxide layer. ### Claim 20 (depends on 16) The semiconductor device as claimed in claim 16, wherein a maximum thickness of the oxide layer is in a range from about 200 nm to about 300 nm.