# US 2025/0096151 A1 · Wire bonding method and apparatus for electromagnetic interference shielding > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0096151 A1 - Document ID: US20250096151A1 - Status: Published application - Kind: A1 - Application number: 18/788,822 - Filed: 2024-07-30 - Published: 2025-03-20 - Earliest claimed: 2016-07-29 - Assignees: Adeia Semiconductor Technologies LLC - Applicants: Adeia Semiconductor Technologies LLC - Inventors: Shaowu Huang; Javier A. Delacruz - Web page: https://patentgrep.com/patent/US20250096151A1 ## CPC - H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons - H10W 42/273: {the arrangements being between laterally adjacent chips, e.g. walls between chips} - H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements} - H10W 74/017: {Auxiliary layers for moulds, e.g. release layers or layers preventing residue} - H10W 74/114: {by a substrate and the encapsulations} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/753: {between laterally-adjacent chips} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Apparatuses relating generally to a microelectronic package having protection from electromagnetic interference are disclosed. In an apparatus thereof, a platform has an upper surface and a lower surface opposite the upper surface and has a ground plane. A microelectronic device is coupled to the upper surface of the platform. Wire bond wires are coupled to the ground plane with a pitch. The wire bond wires extend away from the upper surface of the platform with upper ends of the wire bond wires extending above an upper surface of the microelectronic device. The wire bond wires are spaced apart from one another to provide a fence-like perimeter to provide an interference shielding cage. A conductive layer is coupled to at least a subset of the upper ends of the wire bond wires for electrical conductivity to provide a conductive shielding layer to cover the interference shielding cage. ## Claims ### Claim at position 1 1-19. (canceled) ### Claim 20 A packaged microelectronic device, comprising: a first device disposed on a platform; a second device disposed on the platform; a third device disposed on the platform; a first interference shield comprising a first plurality of wire bond wires, wherein: at least a portion of the first interference shield is disposed between the first device and the second device; and at least a portion of the first interference shield is disposed between the third device and the second device; a second interference shield comprising a second plurality of wire bond wires, wherein: at least a portion of the second interference shield is disposed between the first device and the second device; and at least a portion of the second interference shield is disposed between the third device and the second device; a first spacing between a first adjacent pair of wire bond wires in the first interference shield; and a second spacing between a second adjacent pair of wire bond wires in the second interference shield, wherein the second spacing is different than the first spacing. ### Claim 21 (depends on 20) The packaged microelectronic device of claim 20, wherein the platform is a circuit board. ### Claim 22 (depends on 20) The packaged microelectronic device of claim 20, wherein the platform is a substrate. ### Claim 23 (depends on 20) The packaged microelectronic device of claim 20, wherein the platform is a redistribution layer. ### Claim 24 (depends on 20) The packaged microelectronic device of claim 20, wherein the platform is a silicon substrate. ### Claim 25 (depends on 24) The packaged microelectronic device of claim 24, further comprising a third interference shield comprising a third plurality of wire bond wires, wherein at least a portion of the third interference shield is disposed between the third device and the first device. ### Claim 26 (depends on 20) The packaged microelectronic device of claim 20, wherein: the first spacing is about 1/10th or less than a first wavelength of electromagnetic radiation of a first frequency; and the second spacing is about 1/10th or less than a second wavelength of electromagnetic radiation of a second frequency. ### Claim 27 (depends on 20) The packaged microelectronic device of claim 20, further comprising a fourth device disposed on the platform, wherein at least a portion of the first interference shield is disposed between the first device and the fourth device. ### Claim 28 (depends on 27) The packaged microelectronic device of claim 27, wherein at least a portion of the first interference shield is disposed between the fourth device and the third device. ### Claim 29 (depends on 27) The packaged microelectronic device of claim 27, wherein at least a portion of the second interference shield is disposed between the fourth device and the second device. ### Claim 30 (depends on 20) The packaged microelectronic device of claim 20, further comprising a fourth device disposed on the platform, wherein at least a portion of the second interference shield is disposed between the second device and the fourth device. ### Claim 31 (depends on 30) The packaged microelectronic device of claim 30, wherein at least a portion of the first interference shield is disposed between the fourth device and the first device. ### Claim 32 A packaged microelectronic device, comprising: a first device disposed on a platform; a second device disposed on the platform; a third device disposed on the platform; a first interference shield comprising a first plurality of wire bond wires, wherein: the first interference shield intersects a shortest path between the first device and the second device, and the first interference shield intersects a shortest path between the third device and the second device; a second interference shield comprising a second plurality of wire bond wires, wherein: the second interference shield intersects the shortest path between the first device and the second device, and the second interference shield intersects the shortest path between the third device and the second device; a first spacing between a first adjacent pair of wire bond wires in the first interference shield; and a second spacing between a second adjacent pair of wire bond wires in the second interference shield, wherein the second spacing is larger than the first spacing. ### Claim 33 (depends on 32) The packaged microelectronic device of claim 32, wherein the platform is a circuit board. ### Claim 34 (depends on 32) The packaged microelectronic device of claim 32, wherein the platform is a substrate. ### Claim 35 (depends on 32) The packaged microelectronic device of claim 32, wherein the platform is a redistribution layer. ### Claim 36 (depends on 32) The packaged microelectronic device of claim 32, wherein the platform is a silicon substrate. ### Claim 37 (depends on 36) The packaged microelectronic device of claim 36, further comprising a third interference shield comprising a third plurality of wire bond wires, wherein at least a portion of the third interference shield is disposed between the third device and the first device. ### Claim 38 (depends on 32) The packaged microelectronic device of claim 32, wherein: the first spacing is about 1/10th or less than a first wavelength of electromagnetic radiation of a first frequency; and the second spacing is about 1/10th or less than a second wavelength of electromagnetic radiation of a second frequency. ### Claim 39 A packaged microelectronic device, comprising: a first device disposed on a platform; a second device disposed on the platform; a third device disposed on the platform; a first interference shield comprising a first plurality of wire bond wires, wherein: the first device and the third device are on a first side of the first interference shield; and the second device is on a second side of the first interference shield; a second interference shield comprising a second plurality of wire bond wires, wherein: the first device and the third device are on a first side of the second interference shield; and the second device is on a second side of the second interference shield; a first spacing between a first adjacent pair of wire bond wires in the first interference shield; and a second spacing between a second adjacent pair of wire bond wires in the second interference shield, wherein the second spacing is different than the first spacing.