# US 2025/0096149 A1 · Semiconductor device with a silicon carbide portion and a glass structure and method of manufacturing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0096149 A1 - Document ID: US20250096149A1 - Status: Published application - Kind: A1 - Application number: 18/885,846 - Filed: 2024-09-16 - Published: 2025-03-20 - Earliest claimed: 2023-09-20 - Assignees: Infineon Technologies AG - Applicants: Infineon Technologies AG - Inventors: Rudolf Elpelt; Francisco Javier Santos Rodriguez; Bernd Zippelius; Antonio Vellei; Alexander Breymesser - Web page: https://patentgrep.com/patent/US20250096149A1 ## CPC - H10W 46/00: Marks applied to devices, e.g. for alignment or identification - H10D 8/051: {of Schottky diodes} - H10D 8/411: {PN diodes having planar bodies} - H10D 8/422: {PN diodes having the PN junctions in mesas} - H10D 8/605: {of the trench conductor-insulator-semiconductor barrier type, e.g. trench MOS barrier Schottky rectifiers [TMBS]} - H10D 12/031: {of IGBTs} - H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes} - H10D 30/665: {having edge termination structures} - H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors} - H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)} - H10D 62/8325: {Silicon carbide} - H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)} - H10D 8/60: Schottky-barrier diodes - H10D 62/105: {by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] (IGFETs having LDD or drain extension regions H10D30/601)} - H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions} - H10W 46/503: {Located in scribe lines} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device includes a single-crystalline silicon carbide portion with a first surface, an opposite second surface, and a third surface extending from the first surface in a direction of the second surface. Along the third surface, hydrogen atoms and/or atoms of one or more nonmetal elements other than silicon and having an atomic number greater than six saturate dangling bonds of the silicon carbide portion and/or a passivating coating is in direct contact with the third surface. The semiconductor device further includes a glass structure and an interface layer structure between the third surface and the glass structure. ## Claims ### Claim 1 A semiconductor device, comprising: a single-crystalline silicon carbide portion comprising a first surface, an opposite second surface, and a third surface extending from the first surface in a direction of the second surface, wherein a) along the third surface, hydrogen atoms and/or atoms of one or more nonmetal elements other than silicon and having an atomic number greater than six saturate dangling bonds of the silicon carbide portion and/or b) a passivating coating is in direct contact with the third surface; a glass structure; and an interface layer structure between the third surface and the glass structure. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the one or more nonmetal elements include at least one of nitrogen, oxygen, and phosphorus. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the passivating coating comprises a layer structure that includes at least one of: an oxide layer; a nitride layer; an oxynitride layer; and a carbon-containing layer. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein the third surface includes an inner sidewall of a trench structure laterally surrounding a center portion of the silicon carbide portion. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein the third surface forms at least a portion of a lateral surface connecting an edge of the first surface and an edge of the second surface. ### Claim 6 (depends on 5) The semiconductor device of claim 5, wherein the third surface connects the edge of the first surface and the edge of the second surface. ### Claim 7 (depends on 1) The semiconductor device of claim 1, wherein the silicon carbide portion includes a heavily doped base portion of a first conductivity type and a less heavily doped main layer of the first conductivity type between the first surface and the base portion, and wherein the third surface laterally exposes the main layer and the base portion. ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein the interface layer structure comprises a surface portion on the first surface. ### Claim 9 (depends on 8) The semiconductor device of claim 8, wherein the glass structure comprises a horizontal part formed on the interface layer structure. ### Claim 10 (depends on 9) The semiconductor device of claim 9, further comprising: a first metal structure in direct contact with the first surface of the silicon carbide portion and the interface layer structure. ### Claim 11 (depends on 10) The semiconductor device of claim 10, wherein a first vertical extent of the surface portion of the interface layer structure is at least 80% and at most 120% of a second vertical extent of the first metal structure. ### Claim 12 (depends on 10) The semiconductor device of claim 10, wherein a first vertical extent of the surface portion of the interface layer structure is less than 80% of a second vertical extent of the first metal structure. ### Claim 13 (depends on 12) The semiconductor device of claim 12, wherein a total thickness of the interface layer structure and the horizontal part of the glass structure and the second vertical extent of the first metal structure are equal. ### Claim 14 (depends on 13) The semiconductor device of claim 13, wherein the first metal structure and the horizontal part of the glass structure are laterally separated. ### Claim 15 (depends on 10) The semiconductor device of claim 10, wherein in a lateral direction, the surface portion of the interface layer structure ends at the first metal structure and the first metal structure ends at the surface portion of the interface layer structure. ### Claim 16 (depends on 10) The semiconductor device of claim 10, wherein the surface portion of the interface layer structure and the first metal structure overlap in the vertical direction. ### Claim 17 (depends on 16) The semiconductor device of claim 16, further comprising: a body/anode region of a second conductivity type complementary to the first conductivity type, wherein the silicon carbide portion includes a heavily doped base portion of a first conductivity type and a less heavily doped main layer of the first conductivity type between the first surface and the base portion, wherein the third surface laterally exposes the main layer and the base portion, and wherein the body/anode region is formed between the main layer and the first surface. ### Claim 18 (depends on 17) The semiconductor device of claim 17, wherein the body/anode region is formed at a distance to the interface layer structure and the passivating coating. ### Claim 19 (depends on 17) The semiconductor device of claim 17, further comprising: a field relaxing structure of the second conductivity type laterally surrounding the body/anode region, wherein a net doping of the field relaxing structure is lower than a net doping in the body/anode region. ### Claim 20 (depends on 19) The semiconductor device of claim 19, wherein the field relaxing structure is in direct contact with the interface layer structure or the passivating coating. ### Claim 21 (depends on 19) The semiconductor device of claim 19, wherein the field relaxing structure is formed at a distance to the interface layer structure and the passivating coating. ### Claim 22 (depends on 19) The semiconductor device of claim 19, wherein the field relaxing structure comprises a single field relaxing ring. ### Claim 23 (depends on 19) The semiconductor device of claim 19, wherein the field relaxing structure comprises a plurality of laterally separated field relaxing rings. ### Claim 24 (depends on 19) The semiconductor device of claim 19, further comprising: a surface layer of the first conductivity type between the first surface and the field relaxing structure. ### Claim 25 (depends on 19) The semiconductor device of claim 19, wherein the field relaxing structure comprises a plurality of field relaxing rings and a supplementary structure, and wherein the supplementary structure is in direct contact with the field relaxing rings and has a lower net doping than the field relaxing rings. ### Claim 26 (depends on 25) The semiconductor device of claim 25, wherein the supplementary structure comprises a plurality of supplementary rings, each supplementary ring formed between neighboring ones of the field relaxing rings or between an innermost one of the field relaxing rings and the body/anode region. ### Claim 27 A method of manufacturing a semiconductor device, the method comprising: forming a separation trench in a main surface of a single-crystalline silicon carbide layer, wherein the separation trench surrounds a die portion of the silicon carbide layer; treating a first sidewall of the separation trench in a conditioning process such that dangling bonds of the silicon carbide layer are passivated; forming an interface layer on the first sidewall of the separation trench; forming a glass fill structure in the separation trench; and separating the silicon carbide layer along a vertical separation line parallel to the separation trench. ### Claim 28 (depends on 27) The method of claim 27, wherein the vertical separation line runs through and along the separation trench. ### Claim 29 (depends on 27) The method of claim 27, wherein treating the first sidewall of the separation trench comprises a plasma-based flash passivation. ### Claim 30 (depends on 27) The method of claim 27, wherein treating the first sidewall of the separation trench comprises depositing a passivation coating using a precursor material containing silicon as a main component. ### Claim 31 (depends on 27) The method of claim 27, wherein forming the glass fill structure comprises pressing a glass material into the separation trench. ### Claim 32 (depends on 27) The method of claim 27, further comprising: forming a contact layer in a contact section of the main surface, wherein the contact layer and the silicon carbide layer form an ohmic contact or a Schottky contact; and forming a principal layer on the contact layer, wherein the principal layer comprises at least one of aluminum and copper. ### Claim 33 (depends on 32) The method of claim 32, wherein the separation trench is formed after forming the principal layer. ### Claim 34 (depends on 32) The method of claim 32, wherein the separation trench is formed after forming the contact layer and the principal layer is formed after forming the glass fill structure. ### Claim 35 (depends on 34) The method of claim 34, wherein a section of the principal layer is formed on a section of the glass fill structure. ### Claim 36 (depends on 27) The method of claim 27, further comprising: thinning, before separating, the silicon carbide layer from a side opposite to the main surface, wherein the glass fill structure is exposed. ### Claim 37 (depends on 27) The method of claim 27, further comprising: forming gate electrode structures in the silicon carbide layer, wherein forming the gate electrode structures comprises: forming gate trenches extending from the main surface into the silicon carbide layer; and forming gate electrodes in the gate trenches, wherein the separation trench is formed before forming the gate electrodes. ### Claim 38 (depends on 37) The method of claim 37, further comprising: filling the separation trench with an auxiliary material before forming the gate electrodes; and removing the auxiliary material after forming the contact layer.