# US 2025/0096115 A1 · Semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0096115 A1 - Document ID: US20250096115A1 - Status: Published application - Kind: A1 - Application number: 18/961,802 - Filed: 2024-11-27 - Published: 2025-03-20 - Earliest claimed: 2019-03-19 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Hisashi KATO - Web page: https://patentgrep.com/patent/US20250096115A1 ## CPC - H10B 43/10: characterised by the top-view layout - H10W 20/42: Vias, e.g. via plugs - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/35: with cell select transistors, e.g. NAND - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - H10B: ELECTRONIC MEMORY DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract According to one embodiment, a semiconductor memory device includes first and second conductor layers, a first pillar, a first contact, and a source line drive circuit. The first pillar is passing through the second conductor layers. The first pillar includes a first semiconductor layer and a second insulator layer. The first semiconductor layer includes a side surface partially in contact with the first conductor layer. The first contact is passing through the second conductor layers. The first contact includes a third conductor layer and a third insulator layer. The third conductor layer includes a side surface partially in contact with the first conductor layer. The source line drive circuit is electrically coupled to the first conductor layer via the first contact. ## Claims ### Claim 1 A semiconductor memory device, comprising: a first conductor layer provided via a first insulator layer above a substrate; a stacked structure in which a plurality of second conductor layers are stacked above the first conductor layer and spaced apart from each other in a first direction; a pillar passing through the second conductor layers along the first direction, and including a first semiconductor layer electrically coupled to the first conductor layer and a second insulator layer provided between the first semiconductor layer and the second conductor layers of the stacked structure, intersections of the pillar with the second conductor layers functioning as memory cell transistors; a plurality of insulating members provided in a plurality of slits each extending in a second direction intersecting the first direction in the second conductor layers of the stacked structure and dividing the stacked structure into a plurality of regions in a third direction intersecting the first direction and the second direction; a plurality of conductive members passing through the second conductor layers along the first direction in which top surfaces thereof differing in height from a top surface of the pillar, each of the conductive members including a third conductor layer partially in contact with the first conductor layer and a third insulator layer provided between the third conductor layer and the second conductor layers of the stacked structure; and a plurality of upper contacts provided on third conductor layers of first and second conductive members among the conductive members, the first and second conductive members being aligned in the second direction, wherein no upper contact is provided on third conductor layers of third and fourth conductive members among the conductive members, the third and fourth conductive members being aligned in the second direction, and the first to fourth conductive members are arranged within a region between two insulating members adjacent in the third direction among the insulating members, positions of the first and second conductive members being closer to a central position between the two insulating members than positions of the third and fourth conductive members along the third direction. ### Claim 2 (depends on 1) The device of claim 1, wherein the third conductor layer contains tungsten. ### Claim 3 (depends on 1) The device of claim 1, wherein the third insulator layer contains silicon oxide. ### Claim 4 (depends on 1) The device of claim 1, wherein the top surfaces of the conductive members are higher than the top surface of the pillar. ### Claim 5 (depends on 1) The device of claim 1, wherein the third conductor layers of the third and fourth conductive members are electrically coupled to each other on a side of lower ends of the third conductor layers. ### Claim 6 (depends on 1) The device of claim 1, wherein the first conductor layer functions as a source layer and the third conductor layers of the third and fourth conductive members are electrically coupled to each other in a same level as the source layer in the first direction. ### Claim 7 (depends on 1) The device of claim 1, wherein a portion of the stacked structure within the region between the two insulating members is provided between the first to fourth conductive members. ### Claim 8 (depends on 1) The device of claim 1, wherein a plurality of types of insulators are provided in the slits. ### Claim 9 (depends on 8) The device of claim 8, wherein the plurality of types of insulators in the slits include silicon oxide and silicon nitride formed on a side wall of the silicon oxide. ### Claim 10 (depends on 1) The device of claim 1, further comprising a drive circuit provided below the first conductor layer. ### Claim 11 A semiconductor memory device, comprising: a first conductor layer provided via a first insulator layer above a substrate; a stacked structure in which a plurality of second conductor layers are stacked above the first conductor layer and spaced apart from each other in a first direction; a pillar passing through the second conductor layers along the first direction, and including a first semiconductor layer electrically coupled to the first conductor layer and a second insulator layer provided between the first semiconductor layer and the second conductor layers of the stacked structure, intersections of the pillar with the second conductor layers functioning as memory cell transistors; a plurality of insulating members provided in a plurality of slits each extending in a second direction intersecting the first direction in the second conductor layers of the stacked structure and dividing the stacked structure into a plurality of regions in a third direction intersecting the first direction and the second direction; a plurality of conductive members passing through the second conductor layers along the first direction in which top surfaces thereof differing in height from a top surface of the pillar, each of the conductive members including a third conductor layer partially in contact with the first conductor layer and a third insulator layer provided between the third conductor layer and the second conductor layers of the stacked structure; and an upper contact provided on the third conductor layer of a first one of the conductive members, wherein no upper contact is provided on the third conductor layer of a second one of the conductive members, the first one and the second one of the conductive members both passing through the stacked structure within a first region among the regions positioned between two insulating members adjacent in the third direction among the insulating members, a portion of the stacked structure within the first region is provided between the first one and the second one of the conductive members, and a position of the first one of the conductive members is closer to a central position between the two insulating members than a position of the second one of the conductive members along the third direction within the first region. ### Claim 12 (depends on 11) The device of claim 11, wherein the third conductor layer contains tungsten. ### Claim 13 (depends on 11) The device of claim 11, wherein the third insulator layer contains silicon oxide. ### Claim 14 (depends on 11) The device of claim 11, wherein the top surfaces of the conductive members are higher than the top surface of the pillar. ### Claim 15 (depends on 11) The device of claim 11, wherein any upper contact is not provided on respective third conductor layers of two or more conductive members among the conductive members and the third conductor layers of the two or more conductive members are electrically coupled to each other on a side of lower ends of the third conductor layers. ### Claim 16 (depends on 15) The device of claim 15, wherein the two or more conductive members are aligned in the second direction. ### Claim 17 (depends on 15) The device of claim 15, wherein the first conductor layer functions as a source layer and the third conductor layers of the two or more conductive members are electrically coupled to each other in a same level as the source layer in the first direction. ### Claim 18 (depends on 11) The device of claim 11, wherein a plurality of types of insulators are provided in the slits. ### Claim 19 (depends on 18) The device of claim 18, wherein the plurality of types of insulators in the slits include silicon oxide and silicon nitride formed on a side wall of the silicon oxide. ### Claim 20 (depends on 11) The device of claim 11, further comprising a drive circuit provided below the first conductor layer.