# US 2025/0096103 A1 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0096103 A1 - Document ID: US20250096103A1 - Status: Published application - Kind: A1 - Application number: 18/825,412 - Filed: 2024-09-05 - Published: 2025-03-20 - Earliest claimed: 2023-09-18 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Sunjun KIM - Web page: https://patentgrep.com/patent/US20250096103A1 ## CPC - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/611: {for connecting multiple chips together} - H10W 70/635: {Through-vias} - H10W 70/685: comprising multiple insulating layers - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 74/111: {the semiconductor body being completely enclosed} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device includes a base substrate and a semiconductor chip disposed on the base substrate. The base substrate includes a core substrate, first interconnection substrates disposed on a first surface of the core substrate and a second surface opposite to the first surface, a first through-electrode penetrating the core substrate, a second through-electrode penetrating the core substrate and the first interconnection substrates, having a same central axis as the first through-electrode, and having a width narrower than a width of the first through-electrode, and a first insulating layer disposed between the first through-electrode and the second through-electrode and surrounding at least a portion of a side surface of the second through-electrode. ## Claims ### Claim 1 A semiconductor device, comprising: a base substrate; and a semiconductor chip disposed on the base substrate, wherein the base substrate includes: a core substrate; a plurality of first interconnection substrates disposed on a first surface of the core substrate and a second surface of the core substrate opposite to the first surface; a first through-electrode penetrating the core substrate; a second through-electrode penetrating the core substrate and the first interconnection substrates, wherein the second through-electrode has a same central axis as the first through-electrode, and has a width narrower than a width of the first through-electrode; and a first insulating layer disposed between the first through-electrode and the second through-electrode and surrounding at least a portion of a side surface of the second through-electrode, and wherein the semiconductor chip is electrically connected to at least a portion of the first and second through-electrodes. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the base substrate further includes a plurality of second interconnection substrates disposed on the first interconnection substrates, wherein the first interconnection substrates include a first interconnection layer electrically connected to the first through-electrode, and wherein the second interconnection substrates include a second interconnection layer electrically connected to the second through-electrode. ### Claim 3 (depends on 2) The semiconductor device of claim 2, wherein the first interconnection substrates further include a first via plug connecting the first interconnection layer to the second interconnection layer, and wherein the second interconnection layer is electrically connected to the first through-electrode through the first via plug. ### Claim 4 (depends on 2) The semiconductor device of claim 2, wherein at least a portion of the first insulating layer extends into the first interconnection substrates, and wherein an upper surface of the first insulating layer is substantially on a same level as a level of an upper surface of the first interconnection layer. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein, in a plan view, the first through-electrode has a circular cross-sectional surface which is hollow and has a first thickness, and the second through-electrode has a circular cross-sectional surface. ### Claim 6 (depends on 5) The semiconductor device of claim 5, wherein the first thickness of the circular cross-sectional surface of the first through-electrode is about 10 μm to about 100 μm. ### Claim 7 (depends on 5) The semiconductor device of claim 5, wherein the circular cross-sectional surface of the second through-electrode has a horizontal width of about 30 μm to about 100 μm. ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein, in a plan view, the first through-electrode has a quadrangular cross-sectional surface which is hollow and has a uniform thickness, and the second through-electrode has a quadrangular cross-sectional surface. ### Claim 9 (depends on 1) The semiconductor device of claim 1, wherein, in a plan view, the first through-electrode has a rounded quadrangular cross-sectional surface which is hollow and has a uniform thickness, and the second through-electrode has a rounded quadrangular cross-sectional surface. ### Claim 10 (depends on 1) The semiconductor device of claim 1, wherein the first through-electrode has a uniform width along the core substrate, and wherein the second through-electrode has a uniform width along the core substrate and the first interconnection substrates. ### Claim 11 (depends on 1) The semiconductor device of claim 1, wherein the base substrate further includes: a plurality of second interconnection substrates disposed on the first interconnection substrates; a third through-electrode penetrating the core substrate and the first and second interconnection substrates, wherein the third through-electrode has the same central axis as the second through-electrode, and has a width narrower than the width of the second through-electrode; and a second insulating layer disposed between the second through-electrode and the third through-electrode and surrounding at least a portion of the third through-electrode. ### Claim 12 (depends on 11) The semiconductor device of claim 11, wherein at least a portion of the second insulating layer extends into the second interconnection substrates. ### Claim 13 (depends on 11) The semiconductor device of claim 11, wherein an external side surface of the first through-electrode is spaced apart from the central axis by a first distance, an external side surface of the second through-electrode is spaced apart from the central axis by a second distance smaller than the first distance, and an external side surface of the third through-electrode is spaced apart from the central axis by a third distance smaller than the second distance, and wherein the first distance is about 45 μm to about 350 μm, the second distance is about 30 μm to about 200 μm, and the third distance is about 15 μm to about 50 μm. ### Claim 14 A semiconductor device, comprising: a base substrate; and a semiconductor chip disposed on the base substrate, wherein the base substrate includes: a core substrate; a plurality of first interconnection substrates disposed on a first surface of the core substrate and a second surface of the core substrate opposite to the first surface; a first via hole penetrating the core substrate; a second via hole penetrating the core substrate and the first interconnection substrates, wherein the second via hole has a same central axis as the first via hole, and has a width narrower than a width of the first via hole; a first conductive plug disposed on an internal wall of the first via hole; and a second conductive plug disposed in at least a portion of the second via hole. ### Claim 15 (depends on 14) The semiconductor device of claim 14, wherein the second conductive plug fills the second via hole, and wherein the semiconductor device further includes a first insulating film disposed in the first via hole and disposed between the first conductive plug and the second conductive plug. ### Claim 16 (depends on 15) The semiconductor device of claim 15, wherein the second conductive plug is disposed on an internal wall of the second via hole, and wherein the semiconductor device further includes: a plurality of second interconnection substrates disposed on the first interconnection substrates; a third via hole penetrating the core substrate and the first and second interconnection substrates, wherein the third via hole has the same central axis as the first and second via holes, and has a width narrower than the width of the second via hole; a third conductive plug filling the third via hole; and a second insulating film disposed in the second via hole and disposed between the second conductive plug and the third conductive plug. ### Claim 17 (depends on 16) The semiconductor device of claim 16, wherein, in a plan view, the first, second, and third via holes have a step difference in a direction away from the central axis. ### Claim 18 A semiconductor device, comprising: a base substrate including a core substrate, a plurality of first interconnection substrates disposed on each of a first surface of the core substrate and a second surface of the core substrate opposite to the first surface and including a plurality of first interconnection layers, a plurality of second interconnection substrates disposed on the first interconnection substrates and including a plurality of second interconnection layers, and a plurality of first through-via structures penetrating at least a portion of the core substrate, the first interconnection substrates, and the second interconnection substrates; and a semiconductor chip disposed on the base substrate and electrically connected to at least a portion of the first and second interconnection layers, wherein at least a portion of the plurality of first through-via structures includes: a first through-electrode penetrating the core substrate and in contact with the first interconnection layers; a second through-electrode penetrating the core substrate and the first interconnection substrates, wherein the second through-electrode has a same central axis as the first through-electrode and has a width narrower than a width of the first through-electrode, and is in contact with the second interconnection layers; and a first insulating layer disposed between the first through-electrode and the second through-electrode and substantially on a same level as the first interconnection layers. ### Claim 19 (depends on 18) The semiconductor device of claim 18, wherein the base substrate further includes a plurality of third interconnection substrates disposed on the second interconnection substrates and including a plurality of third interconnection layers, and wherein at least a portion of the plurality of first through-via structures further includes: a third through-electrode penetrating the core substrate, the first interconnection substrates, and the second interconnection substrates, wherein the third through-electrode has the same central axis as the second through-electrode, has a width narrower than the width of the second through-electrode, and is in contact with the third interconnection layers; and a second insulating layer disposed between the second through-electrode and the third through-electrode and substantially on a same level as a level of the second interconnection layers. ### Claim 20 (depends on 19) The semiconductor device of claim 19, wherein the base substrate further includes a fourth interconnection layer disposed on the third interconnection substrates, and a second through-via structure on a level different from a level of the first through-via structure, and wherein the second through-via structure includes: a first through-plug penetrating the second interconnection substrates and in contact with the second interconnection layers and the third interconnection layers; a second through-plug penetrating the first interconnection substrates, the second interconnection substrates, and the third interconnection substrates, wherein the second through-plug has the same central axis as the first through-plug and has a width narrower than the first through-plug, and is in contact with the first interconnection layers and the fourth interconnection layers; and a third insulating layer disposed between the first through-plug and the second through-plug and substantially on a same level as a level of the third interconnection layers. ### Claim at position 21 21-30. (canceled)