# US 2025/0095984 A1 · In-situ sidewall passivation toward the bottom of high aspect ratio features > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0095984 A1 - Document ID: US20250095984A1 - Status: Published application - Kind: A1 - Application number: 18/370,536 - Filed: 2023-09-20 - Published: 2025-03-20 - Earliest claimed: 2023-09-20 - Assignees: Applied Materials, Inc. - Applicants: Applied Materials, Inc. - Inventors: Sonam Dorje Sherpa; Iljo Kwak; Kenji Takeshita; Alok Ranjan - Web page: https://patentgrep.com/patent/US20250095984A1 ## CPC - H10P 14/6334: {using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329)} - H10P 14/6681: {the precursor containing a compound comprising Si} - H10P 50/283: {by chemical means} - H10P 50/642: {Chemical etching} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract Methods of semiconductor processing may include providing a silicon-containing precursor and an oxygen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. A feature may extend through one or more layers of material disposed on the substrate. The methods may include forming plasma effluents of the silicon-containing precursor and the oxygen-containing precursor. The methods may include contacting the substrate with the plasma effluents of the silicon-containing precursor and the oxygen-containing precursor. The contacting may form a silicon-and-oxygen-containing material on at least a bottom portion of the feature. A temperature in the processing region may be maintained at less than or about 0° C. ## Claims ### Claim 1 A semiconductor processing method comprising: providing a silicon-containing precursor and an oxygen-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate is housed within the processing region, and wherein a feature extends through one or more layers of material disposed on the substrate; forming plasma effluents of the silicon-containing precursor and the oxygen-containing precursor; and contacting the substrate with the plasma effluents of the silicon-containing precursor and the oxygen-containing precursor, wherein the contacting forms a silicon-and-oxygen-containing material on at least a bottom portion of the feature, and wherein a temperature in the processing region is maintained at less than or about 0° C. ### Claim 2 (depends on 1) The semiconductor processing method of claim 1, wherein the silicon-containing precursor further comprises a halogen. ### Claim 3 (depends on 1) The semiconductor processing method of claim 1, wherein the silicon-containing precursor comprises silicon tetrafluoride (SiF4). ### Claim 4 (depends on 1) The semiconductor processing method of claim 1, wherein the oxygen-containing precursor comprises diatomic oxygen (O2). ### Claim 5 (depends on 1) The semiconductor processing method of claim 1, wherein the feature is characterized by a depth of greater than or about 150 nm. ### Claim 6 (depends on 1) The semiconductor processing method of claim 1, wherein the one or more layers of material comprise alternating layers of oxygen-containing material and nitrogen-containing material. ### Claim 7 (depends on 1) The semiconductor processing method of claim 1, wherein the plasma effluents of the silicon-containing precursor and the oxygen-containing precursor are formed at a plasma power of less than or about 2,000 W. ### Claim 8 (depends on 1) The semiconductor processing method of claim 1, further comprising: applying a bias power while contacting the substrate with the plasma effluents of the silicon-containing precursor and the oxygen-containing precursor. ### Claim 9 (depends on 8) The semiconductor processing method of claim 8, wherein the bias power is less than or about 2,500 W. ### Claim 10 (depends on 1) The semiconductor processing method of claim 1, further comprising: prior to providing the silicon-containing precursor and the oxygen-containing precursor to the processing region, etching the feature in the substrate. ### Claim 11 A semiconductor processing method comprising: providing a silicon-and-halogen-containing precursor and an oxygen-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate is housed within the processing region, and wherein a feature extends through one or more layers of material disposed on the substrate; forming plasma effluents of the silicon-and-halogen-containing precursor and the oxygen-containing precursor; and contacting the substrate with the plasma effluents of the silicon-and-halogen-containing precursor and the oxygen-containing precursor, wherein the contacting forms a silicon-oxygen-and-halogen-containing material on at least a bottom portion of the feature. ### Claim 12 (depends on 11) The semiconductor processing method of claim 11, wherein a flow rate ratio of the silicon-and-halogen-containing precursor relative to the oxygen-containing precursor is greater than or about 10:1. ### Claim 13 (depends on 11) The semiconductor processing method of claim 11, wherein a flow rate of the oxygen-containing precursor is less than or about 25 sccm. ### Claim 14 (depends on 11) The semiconductor processing method of claim 11, wherein the silicon-oxygen-and-halogen-containing material is formed in the same semiconductor processing chamber in which the feature is etched. ### Claim 15 (depends on 11) The semiconductor processing method of claim 11, wherein the silicon-oxygen-and-halogen-containing material is physisorbed on the feature. ### Claim 16 (depends on 11) The semiconductor processing method of claim 11, wherein a temperature in the processing region is maintained at less than or about −20° C. ### Claim 17 (depends on 11) The semiconductor processing method of claim 11, wherein a pressure in the processing region is maintained at less than or about 100 mTorr. ### Claim 18 A semiconductor processing method comprising: providing one or more etchant precursors to a processing region of a semiconductor processing chamber, wherein a substrate is housed within the processing region, and wherein the substrate comprises one or more layers of material; contacting the substrate with the one or more etchant precursors, wherein the contacting etches a feature into the one or more layers of material; halting a flow of the one or more etchant precursors; providing a silicon-containing precursor and an oxygen-containing precursor to the processing region; forming plasma effluents of the silicon-containing precursor and the oxygen-containing precursor; and 12 contacting the substrate with the plasma effluents of the silicon-containing precursor and the oxygen-containing precursor, wherein the contacting forms a passivation material on at least a bottom portion of the feature, and wherein a temperature in the processing region is maintained at less than or about 0° C. ### Claim 19 (depends on 18) The semiconductor processing method of claim 18, wherein the feature is characterized by a depth of greater than or about 300 nm. ### Claim 20 (depends on 18) The semiconductor processing method of claim 18, wherein the passivation material comprises a silicon-oxygen-and-halogen-containing material.