# US 2025/0095757 A1 · Neighbor plane disturb (npd) detection for memory devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0095757 A1 - Document ID: US20250095757A1 - Status: Published application - Kind: A1 - Application number: 18/369,296 - Filed: 2023-09-18 - Published: 2025-03-20 - Earliest claimed: 2023-09-18 - Assignees: Western Digital Technologies, Inc. - Applicants: Western Digital Technologies, Inc. - Inventors: Sai Gautham Thoppa; Parth Amin; Long Pham - Web page: https://patentgrep.com/patent/US20250095757A1 ## CPC - G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/10: Programming or data input circuits - G11C 16/102: {External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators} - G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory device includes a plurality of memory cells arranged in a plurality of planes and control circuitry configured to perform a multi-plane programming operation in which memory cells in each of the plurality of planes are programmed in a single programming operation. To perform the multi-plane programming operation, the control circuity is configured to detect a neighbor plane disturb (NPD) defect during the multi-plane programming operation, in response to detecting the NPD defect, terminate the multi-plane programming operation prior to completing the multi-plane programming operation, and identify which plane of the plurality of planes includes the NPD defect. ## Claims ### Claim 1 A memory device, comprising: a plurality of memory cells arranged in a plurality of planes; and control circuitry configured to perform a multi-plane programming operation in which memory cells in each of the plurality of planes are programmed in a single programming operation, wherein, to perform the multi-plane programming operation, the control circuity is configured to detect a neighbor plane disturb (NPD) defect during the multi-plane programming operation, in response to detecting the NPD defect, terminate the multi-plane programming operation prior to completing the multi-plane programming operation, and identify which plane of the plurality of planes includes the NPD defect. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the control circuitry is configured to detect the NPD defect based on a program voltage applied to a word line of the memory device. ### Claim 3 (depends on 2) The memory device of claim 2, wherein the control circuitry is configured to detect the NPD defect based on a determination of whether the program voltage reaches a target voltage level within a predetermined period. ### Claim 4 (depends on 2) The memory device of claim 2, wherein the word line corresponds to a word line coupled to the memory cells in each of the plurality of planes. ### Claim 5 (depends on 1) The memory device of claim 1, wherein, in response to detecting the NPD defect, the control circuitry is configured terminate the multi-plane programming operation prior to completing a maximum number of programming loops associated with the multi-plane programming operation. ### Claim 6 (depends on 1) The memory device of claim 1, wherein, to identify which plane of the plurality of planes includes the NPD defect, the control circuitry is configured to (i) transition from a multi-plane programming mode to a single plane programming mode and (ii) sequentially perform single plane programming operations on each of the plurality of planes. ### Claim 7 (depends on 6) The memory device of claim 6, wherein, during the single plane programming operations, the control circuitry is configured to identify whether a selected plane has the NPD defect based on a program voltage applied to a word line of the memory device. ### Claim 8 A method for operating a memory device including a plurality of memory cells arranged in a plurality of planes, the method comprising: performing a multi-plane programming operation in which memory cells in each of the plurality of planes are programmed in a single programming operation, wherein performing the multi-plane programming operation includes detecting a neighbor plane disturb (NPD) defect during the multi-plane programming operation, in response to detecting the NPD defect, terminating the multi-plane programming operation prior to completing the multi-plane programming operation, and identifying which plane of the plurality of planes includes the NPD defect. ### Claim 9 (depends on 8) The method of claim 8, further comprising detecting the NPD defect based on a program voltage applied to a word line of the memory device. ### Claim 10 (depends on 9) The method of claim 9, further comprising detecting the NPD defect based on a determination of whether the program voltage reaches a target voltage level within a predetermined period. ### Claim 11 (depends on 9) The method of claim 9, wherein the word line corresponds to a word line coupled to the memory cells in each of the plurality of planes. ### Claim 12 (depends on 8) The method of claim 8, further comprising, in response to detecting the NPD defect, terminating the multi-plane programming operation prior to completing a maximum number of programming loops associated with the multi-plane programming operation. ### Claim 13 (depends on 8) The method of claim 8, wherein identifying which plane of the plurality of planes includes the NPD defect includes (i) transitioning from a multi-plane programming mode to a single plane programming mode and (ii) sequentially performing single plane programming operations on each of the plurality of planes. ### Claim 14 (depends on 13) The method of claim 13, further comprising, during the single plane programming operations, identifying whether a selected plane has the NPD defect based on a program voltage applied to a word line of the memory device. ### Claim 15 A memory device, comprising: a plurality of memory cells arranged in a plurality of planes; and control means for performing a multi-plane programming operation in which memory cells in each of the plurality of planes are programmed in a single programming operation, wherein, to perform the multi-plane programming operation, the control means detects a neighbor plane disturb (NPD) defect during the multi-plane programming operation, in response to detecting the NPD defect, terminates the multi-plane programming operation prior to completing the multi-plane programming operation, and identifies which plane of the plurality of planes includes the NPD defect. ### Claim 16 (depends on 15) The memory device of claim 15, wherein the control means detects the NPD defect based on whether a program voltage applied to a word line of the memory device reaches a target voltage level within a predetermined period. ### Claim 17 (depends on 16) The memory device of claim 16, wherein the word line corresponds to a word line coupled to the memory cells in each of the plurality of planes. ### Claim 18 (depends on 15) The memory device of claim 15, wherein, in response to detecting the NPD defect, the control means terminates the multi-plane programming operation prior to completing a maximum number of programming loops associated with the multi-plane programming operation. ### Claim 19 (depends on 15) The memory device of claim 15, wherein, to identify which plane of the plurality of planes includes the NPD defect, the control means (i) transitions from a multi-plane programming mode to a single plane programming mode and (ii) sequentially performs single plane programming operations on each of the plurality of planes. ### Claim 20 (depends on 19) The memory device of claim 19, wherein, during the single plane programming operations, the control means identifies whether a selected plane has the NPD defect based on a program voltage applied to a word line of the memory device.