# US 2025/0095754 A1 · Memory device, memory system, and operating method of memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0095754 A1 - Document ID: US20250095754A1 - Status: Published application - Kind: A1 - Application number: 18/804,617 - Filed: 2024-08-14 - Published: 2025-03-20 - Earliest claimed: 2023-09-19 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Tongsung Kim; Seonkyoo Lee; Younggyu Lee; Taesung Lee - Web page: https://patentgrep.com/patent/US20250095754A1 ## CPC - G11C 16/32: Timing circuits - H03K 5/1565: {the output pulses having a constant duty cycle} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/10: Programming or data input circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C: STATIC STORES (semiconductor memory devices H10B) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Provided is a memory device including a first pad configured to receive a read enable signal from a memory controller, a second pad configured to receive a read duty cycle correct command signal, a first duty correction circuit configured to perform a read duty cycle correct operation, based on the read duty cycle correct command received from the memory controller, when the read enable signal is received, and output a data strobe signal generated based on the read duty cycle correct operation, and a second duty correction circuit configured to receive the data strobe signal from the first duty correction circuit, generate a divided data strobe signal by dividing the received data strobe signal, and compare the received data strobe signal with the divided data strobe signal to perform a write duty cycle correct operation. ## Claims ### Claim 1 A memory device comprising: a first pad configured to receive a read enable signal from a memory controller; a second pad configured to receive a read duty cycle correct command signal; a first duty correction circuit configured to perform a read duty cycle correct operation, based on the read duty cycle correct command signal received from the memory controller, when the read enable signal is received, and output a data strobe signal generated based on the read duty cycle correct operation; and a second duty correction circuit configured to receive the data strobe signal from the first duty correction circuit and generate a divided data strobe signal by dividing the received data strobe signal, wherein the second duty correction circuit is further configured to divide the received data strobe signal, based on preset criteria, correct a first duty between a first rising edge and a second falling edge of the divided data strobe signal, and correct a second duty between a first falling edge and the second falling edge of the divided data strobe signal. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the second duty correction circuit comprises: a first corrector configured to correct a duty cycle of the divided data strobe signal, based on a first duty cycle ratio between the first rising edge and a second rising edge of the received data strobe signal; and a second corrector configured to correct the duty cycle of the divided data strobe signal, based on a second duty cycle ratio between the first falling edge and the second falling edge of the received data strobe signal. ### Claim 3 (depends on 2) The memory device of claim 2, wherein the second duty correction circuit further comprises: a third pad configured to receive the data strobe signal from the first duty correction circuit; and a divider configured to divide the received data strobe signal. ### Claim 4 (depends on 2) The memory device of claim 2, wherein the second duty correction circuit further comprises a buffer configured to receive the data strobe signal from the first duty correction circuit, and the second duty correction circuit is further configured to correct the duty cycle of the divided data strobe signal when the buffer is activated. ### Claim 5 (depends on 2) The memory device of claim 2, wherein the second duty correction circuit is further configured to divide the received data strobe signal during the read duty cycle correct operation performed in the first duty correction circuit. ### Claim 6 (depends on 1) The memory device of claim 1, wherein the second duty correction circuit is further configured to correct a duty cycle of the divided data strobe signal during the read duty cycle correct operation. ### Claim 7 (depends on 1) The memory device of claim 1, further comprising a plurality of dies each including the first duty correction circuit and the second duty correction circuit, wherein the second duty correction circuit included in each of the plurality of dies is configured to receive as an input a data strobe signal output from the first duty correction circuit of at least one of the plurality of dies. ### Claim 8 (depends on 1) The memory device of claim 1, wherein the first duty correction circuit comprises a short path switch directly connected to the data strobe signal of the second duty correction circuit. ### Claim 9 An operating method of a memory device, the method comprising: receiving a read duty cycle correct command and a read enable signal from a memory controller; when the read enable signal is received, performing a read duty cycle correct operation, based on the read duty cycle correct command, and outputting a data strobe signal, based on the read duty cycle correct operation; and receiving the output data strobe signal, dividing the received data strobe signal, and performing a write duty cycle correct operation, wherein the performing of the write duty cycle correct operation comprises dividing the data strobe signal, based on preset criteria, and correcting a duty cycle of the divided data strobe signal, based on a first rising edge and a first falling edge of the received data strobe signal. ### Claim 10 (depends on 9) The operating method of claim 9, wherein the performing of the write duty cycle correct operation comprises: correcting the duty cycle of the divided data strobe signal, based on a first duty cycle ratio between the first rising edge and a second rising edge of the received data strobe signal; and correcting the duty cycle of the divided data strobe signal, based on a second duty cycle ratio between a first falling edge and a second falling edge of the received data strobe signal. ### Claim 11 (depends on 9) The operating method of claim 9, wherein the performing of the write duty cycle correct operation further comprises: receiving the output data strobe signal through a third pad; and correcting a duty cycle of the data strobe signal received through the third pad. ### Claim 12 (depends on 9) The operating method of claim 9, wherein the performing of the write duty cycle correct operation further comprises correcting the duty cycle of the divided data strobe signal when a buffer configured to receive the output data strobe signal is activated. ### Claim at position 13 13-15. (canceled) ### Claim 16 A memory system comprising: a memory controller configured to generate a read duty cycle correct command and a read enable signal; and a memory device configured to perform a training operation with respect to a read signal and a write signal, wherein the memory device comprises: a first pad configured to receive the read enable signal from the memory controller; a second pad configured to receive a read duty cycle correct command signal; a first duty correction circuit configured to perform a read duty cycle correct operation, based on the read duty cycle correct command signal received from the memory controller, when the read enable signal is received, and output a data strobe signal, based on the read duty cycle correct operation; and a second duty correction circuit configured to receive the data strobe signal from the first duty correction circuit and generate a divided data strobe signal by dividing the received data strobe signal, wherein the second duty correction circuit is further configured to divide the received data strobe signal, based on preset criteria, correct a first duty between a first rising edge and a second falling edge of the divided data strobe signal, and correct a second duty between a first falling edge and the second falling edge of the divided data strobe signal. ### Claim 17 (depends on 16) The memory system of claim 16, wherein the second duty correction circuit comprises: a first corrector configured to correct a duty cycle of the divided data strobe signal, based on a first duty cycle ratio between the first rising edge and a second rising edge of the received data strobe signal; and a second corrector configured to correct the duty cycle of the divided data strobe signal, based on a second duty cycle ratio between the first falling edge and the second falling edge of the received data strobe signal. ### Claim 18 (depends on 16) The memory system of claim 16, wherein the second duty correction circuit further comprises: a third pad configured to receive the output data strobe signal; and a divider configured to divide the received data strobe signal. ### Claim 19 (depends on 16) The memory system of claim 16, wherein the second duty correction circuit further comprises a buffer configured to receive the output data strobe signal, and wherein the second duty correction circuit is configured to correct a duty cycle of the divided data strobe signal when the buffer is activated. ### Claim 20 (depends on 16) The memory system of claim 16, wherein the second duty correction circuit is further configured to divide the received data strobe signal during the read duty cycle correct operation performed in the first duty correction circuit. ### Claim 21 (depends on 16) The memory system of claim 16, wherein the second duty correction circuit is further configured to correct a duty cycle of the divided data strobe signal during the read duty cycle correct operation. ### Claim 22 (depends on 16) The memory system of claim 16, further comprising a plurality of dies each including the first duty correction circuit and the second duty correction circuit, wherein the second duty correction circuit included in each of the plurality of dies is configured to receive as an input a data strobe signal output from the first duty correction circuit of at least one of the plurality of dies. ### Claim 23 (depends on 16) The memory system of claim 16, wherein the first duty correction circuit comprises a short path switch directly connected to the data strobe signal of the second duty correction circuit.