# US 2025/0095752 A1 · Semiconductor memory device and memory system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0095752 A1 - Document ID: US20250095752A1 - Status: Published application - Kind: A1 - Application number: 18/821,670 - Filed: 2024-08-30 - Published: 2025-03-20 - Earliest claimed: 2023-09-20 - Applicants: Kioxia Corporation - Inventors: Yoshikazu TAKEYAMA; Keisuke TAKAHASHI - Web page: https://patentgrep.com/patent/US20250095752A1 ## CPC - G11C 16/30: Power supply circuits - G06N 3/0455: Auto-encoder networks; Encoder-decoder networks - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/10: Programming or data input circuits - G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits - G11C 16/16: for erasing blocks, e.g. arrays, words, groups - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C: STATIC STORES (semiconductor memory devices H10B) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS ## Abstract A semiconductor memory device includes a memory cell array, a control circuit, and a voltage generation circuit. The control circuit is configured to perform a first operation to access the memory cell array and then a second operation to access the memory cell array. The voltage generation circuit is configured to generate a first operation voltage, which is supplied from an output terminal of the voltage generation circuit to the memory cell array during the first operation, and a second operation voltage, which is supplied from the output terminal to the memory cell array during the second operation. The control circuit is configured to control the voltage generation circuit to maintain a voltage output from the output terminal to be at the first operation voltage after the first operation until the second operation voltage starts to be supplied to the memory cell array for the second operation. ## Claims ### Claim 1 A semiconductor memory device comprising: a memory cell array; a control circuit configured to perform a first operation to access the memory cell array and then a second operation to access the memory cell array; and a voltage generation circuit configured to generate a first operation voltage, which is supplied to from an output terminal of the voltage generation circuit to the memory cell array during the first operation, and a second operation voltage, which is supplied from the output terminal to the memory cell array during the second operation, wherein the control circuit is configured to control the voltage generation circuit to maintain a voltage output from the output terminal to be at the first operation voltage after the first operation until the second operation voltage starts to be supplied to the memory cell array for the second operation. ### Claim 2 (depends on 1) The semiconductor memory device according to claim 1, wherein the first operation is one of a write operation, a read operation, and an erase operation, and the second operation is the same one of the write operation, the read operation, and the erase operation. ### Claim 3 (depends on 1) The semiconductor memory device according to claim 1, wherein the memory cell array includes a first memory cell and a word line connected to the first memory cell, the first operation is a write operation with respect to the first memory cell, and the first operation voltage is supplied from the output terminal to the word line during the first operation, and the second operation is a write operation with respect to the first memory cell, and the second operation voltage is supplied from the output terminal to the word line during the second operation. ### Claim 4 (depends on 3) The semiconductor memory device according to claim 3, wherein the first operation voltage is a first program voltage and the second operation voltage is a second program voltage different from the first program voltage. ### Claim 5 (depends on 1) The semiconductor memory device according to claim 1, wherein the memory cell array includes a first memory cell and a word line connected to the first memory cell, the first operation is a read operation with respect to a memory cell other than the first memory cell, and the first operation voltage is supplied from the output terminal to the word line during the first operation, and the second operation is a read operation with respect to a memory cell other than the first memory cell, and the second operation voltage is supplied from the output terminal to the word line during the second operation. ### Claim 6 (depends on 5) The semiconductor memory device according to claim 5, wherein the first operation voltage is a read pass voltage, and the second operation voltage is equal to the first operation voltage. ### Claim 7 (depends on 1) The semiconductor memory device according to claim 1, wherein the memory cell array includes a first memory cell, a second memory cell, a first source line connected to the first memory cell, and a second source line connected to the second memory cell, the first operation is an erase operation with respect to the first memory cell, and the first operation voltage is supplied from the output terminal to the first source line during the first operation, and the second operation is a read operation with respect to the second memory cell, and the second operation voltage is supplied from the output terminal to the second source line during the second operation. ### Claim 8 (depends on 7) The semiconductor memory device according to claim 7, wherein the first operation voltage is an erase voltage, and the second operation voltage is equal to the first operation voltage. ### Claim 9 (depends on 1) The semiconductor memory device according to claim 1, wherein the first operation is one of a write operation, a read operation, and an erase operation, and the second operation is another one of the write operation, the read operation, and the erase operation. ### Claim 10 (depends on 1) The semiconductor memory device according to claim 1, wherein the memory cell array includes a first memory cell, a word line connected to the first memory cell, and a source line connected to the first memory cell, the first operation is an erase operation with respect to the first memory cell, and the first operation voltage is supplied from the output terminal to the source line during the first operation, and the second operation is a write operation with respect to the first memory cell, and the second operation voltage is supplied from the output terminal to the word line during the second operation. ### Claim 11 (depends on 1) The semiconductor memory device according to claim 1, wherein the memory cell array includes a first memory cell and a word line connected to the first memory cell, the first operation is an erase operation with respect to the first memory cell, and the first operation voltage is supplied from the output terminal to the source line during the first operation, and the second operation is a write operation with respect to a memory cell other than the first memory cell, and the second operation voltage is supplied from the output terminal to the word line during the second operation. ### Claim 12 (depends on 1) The semiconductor memory device according to claim 1, wherein the control circuit is configured to perform a third operation to access the memory cell array after the second operation, the voltage generation circuit is configured to generate a third operation voltage, which is supplied to from the output terminal of the voltage generation circuit to the memory cell array during the third, and the control circuit is configured to control the voltage generation circuit to maintain the voltage output from the output terminal to be at the second operation voltage after the second operation until the third operation voltage starts to be supplied to the memory cell array for the third operation. ### Claim 13 (depends on 12) The semiconductor memory device according to claim 12, wherein the first operation is one of a write operation, a read operation, and an erase operation, and the second operation is another one of the write operation, the read operation, and the erase operation, and the third operation is still another one of the write operation, the read operation, and the erase operation. ### Claim 14 (depends on 1) The semiconductor memory device according to claim 1, wherein the semiconductor memory device is configured to operate in a first mode and a second mode, in the first mode, the control circuit is configured to control the voltage generation circuit to maintain the voltage output from the output terminal to be at the first operation voltage after the first operation until the second operation voltage starts to be supplied to the memory cell array for the second operation, and in the second mode, the control circuit is configured to control the voltage generation circuit to cause the voltage output from the output terminal to drop from the first operation voltage after the first operation and before the second operation voltage starts to be supplied to the memory cell array for the second operation. ### Claim 15 (depends on 14) The semiconductor memory device according to claim 14, wherein the control circuit is configured to switch an operational mode of the semiconductor memory device to the first mode in response to a first command input from outside of the semiconductor memory device. ### Claim 16 (depends on 15) The semiconductor memory device according to claim 15, wherein the control circuit is configured to switch the operational mode of the semiconductor memory device to the first mode and then perform the first operation, in response to a set of commands including the first command followed by a second command instructing the first operation. ### Claim 17 (depends on 15) The semiconductor memory device according to claim 15, wherein the control circuit is configured to perform the first operation in response to a second command received separately from the first command, from the outside of the semiconductor memory device in the first mode. ### Claim 18 (depends on 1) A memory system comprising: the semiconductor memory device according to claim 1; and a memory controller connectable to a host and configured to control the semiconductor memory device in accordance with a command from the host.