# US 2025/0095751 A1 · Managing power supply in semiconductor devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0095751 A1 - Document ID: US20250095751A1 - Status: Published application - Kind: A1 - Application number: 18/467,047 - Filed: 2023-09-14 - Published: 2025-03-20 - Earliest claimed: 2023-09-14 - Assignees: Macronix International Co., Ltd. - Applicants: Macronix International Co., Ltd. - Inventors: Shin-Jang Shen; Chun-Lien Su; Shih-Chou Juan - Web page: https://patentgrep.com/patent/US20250095751A1 ## CPC - G11C 16/30: Power supply circuits - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Systems, devices, methods, and circuits for managing power supply in semiconductor devices are provided. The semiconductor devices can include 3D NAND flash memory devices with high capacity and/or high performance. In one aspect, a semiconductor device includes: a voltage pump, a pump switch circuit configured to be coupled to the voltage pump, and an interface including a voltage pin coupled to the pump switch circuit. The voltage pump has an input, an output, and a series of pump stages coupled between the input and the output. The pump switch circuit is configured to provide an input voltage received at the voltage pin to a corresponding node in the voltage pump to select a corresponding number of pump stages of the series of pump stages to output a target voltage at the output of the voltage pump. ## Claims ### Claim 1 A semiconductor device, comprising: a voltage pump having an input, an output, and a series of pump stages coupled between the input and the output; a pump switch circuit configured to be coupled to the voltage pump; and an interface comprising a voltage pin coupled to the pump switch circuit, wherein the pump switch circuit is configured to provide an input voltage received at the voltage pin to a corresponding node in the voltage pump to select a corresponding number of pump stages of the series of pump stages to output a target voltage at the output of the voltage pump. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the corresponding number is an integer identical to or larger than 0. ### Claim 3 (depends on 1) The semiconductor device of claim 1, further comprising: a voltage detector; and a control circuit coupled to the voltage detector and the pump switch circuit, wherein the voltage detector is configured to detect a value of the input voltage received at the voltage pin, and wherein the control circuit is configured to: receive the value of the input voltage from the voltage detector, and control the pump switch circuit to be coupled to the corresponding node in the voltage pump based on the value of the input voltage. ### Claim 4 (depends on 3) The semiconductor device of claim 3, wherein the control circuit is configured to: receive a signal indicating the target voltage, and control the pump switch circuit to be coupled to the corresponding node in the voltage pump based on the signal, together with the value of the input voltage. ### Claim 5 (depends on 4) The semiconductor device of claim 4, wherein the target voltage is a first target voltage, and wherein the control circuit is configured to: receive a second signal indicating a second target voltage, and control the pump switch circuit to be coupled to a second corresponding node in the voltage pump based on the second signal and a second input voltage received at the voltage pin. ### Claim 6 (depends on 3) The semiconductor device of claim 3, wherein the pump switch circuit comprises a switch switchable to be coupled to each of a plurality of nodes in the voltage pump, and wherein the plurality of nodes comprises: a first node between the output of the voltage pump and a first pump stage of the series of pump stages, the first pump stage being adjacent to the output of the voltage pump, and a second node between two adjacent pump stages of the series of pump stages. ### Claim 7 (depends on 3) The semiconductor device of claim 3, wherein the interface further comprises: a second voltage pin coupled to the input of the voltage pump and configured to receive a second voltage, wherein the voltage pump is configured to generate an output voltage at the output of the voltage pump based on the series of pump stages and the second voltage. ### Claim 8 (depends on 3) The semiconductor device of claim 3, wherein the interface further comprises a third voltage pin configured to receive a third voltage, wherein the semiconductor device further comprises a second voltage detector coupled to the voltage pin and configured to detect a value of the third voltage received at the third voltage pin, and wherein the control circuit is configured to: receive the value of the third voltage from the second voltage detector, determine whether the value of the third voltage matches a predetermined voltage, and in response to determining that the value of the third voltage fails to match the predetermined voltage, disable receiving the third voltage at the third voltage pin and control the pump switch circuit to be coupled to the corresponding node in the voltage pump based on the value of the input voltage to generate the target voltage. ### Claim 9 (depends on 1) The semiconductor device of claim 1, further comprising: a memory array having an array of memory cells coupled to a plurality of word lines; a decoder coupled to the memory array and configured to select each of the plurality of word lines; and a switch circuit coupled between the decoder and the voltage pump and configured to: generate a set of operation voltages based on the target voltage, and output the set of operation voltages to the decoder, and wherein the decoder is configured to apply the set of operation voltages respectively to corresponding word lines of the plurality of word lines. ### Claim 10 (depends on 1) The semiconductor device of claim 1, wherein the input voltage is in a range of 6 V to 10 V. ### Claim 11 A system, comprising: a memory device comprising a memory array having an array of memory cells coupled to a plurality of word lines; and a controller coupled to the memory device and configured to send a command to the memory device, the command indicating the memory device to perform an operation, wherein the memory device further comprises: a voltage generator comprising a voltage pump having an input, an output, and a series of pump stages coupled between the input and the output; a pump switch circuit configured to be coupled to the voltage pump; and an interface comprising a voltage pin coupled to the pump switch circuit and configured to receive an input voltage, wherein the pump switch circuit is configured to provide the input voltage received at the voltage pin to a corresponding node in the voltage pump to select a corresponding number of pump stages of the series of pump stages to output a target voltage at the output of the voltage pump, and wherein the memory device is configured to perform the operation based on the target voltage outputted at the output of the voltage pump. ### Claim 12 (depends on 11) The system of claim 11, comprising a voltage converter coupled to the memory device, wherein the voltage converter is configured to generate the input voltage based on a reference voltage and provide the input voltage to the voltage pin. ### Claim 13 (depends on 12) The system of claim 12, wherein the voltage converter is coupled to the controller and configured to generate the input voltage based on a signal from the controller, the signal being associated with the command and indicating the input voltage. ### Claim 14 (depends on 11) The system of claim 11, wherein the memory device further comprises: a voltage detector; and a control circuit coupled to the voltage detector and the pump switch circuit, wherein the voltage detector is configured to detect a value of the input voltage received at the voltage pin, wherein the control circuit is configured to: receive a signal from the controller, the signal being associated with the operation and indicating the target voltage, receive the value of the input voltage from the voltage detector, and control the pump switch circuit to be coupled to the corresponding node in the voltage pump based on the value of the input voltage and the signal. ### Claim 15 (depends on 14) The system of claim 14, wherein the target voltage is a first target voltage, and wherein the control circuit is configured to: receive a second signal from the controller, the second signal being associated with a second operation and indicating a second target voltage, and control the pump switch circuit to be coupled to a second corresponding node in the voltage pump based on the second signal and a second input voltage received at the voltage pin. ### Claim 16 (depends on 15) The system of claim 15, wherein the controller is configured to send a control signal to a voltage converter to generate the second input voltage to be provided to the voltage pin. ### Claim 17 (depends on 14) The system of claim 14, wherein the pump switch circuit comprises a switch switchable to be coupled to each of a plurality of nodes in the voltage pump, and wherein the plurality of nodes comprises: a first node between the output of the voltage pump and a first pump stage of the series of pump stages, the first pump stage being adjacent to the output of the voltage pump, and a second node between two adjacent voltage pumps of the series of pump stages. ### Claim 18 (depends on 14) The system of claim 14, wherein the interface further comprises: a second voltage pin coupled to the input of the voltage pump and configured to receive a second voltage, wherein the voltage pump is configured to generate an output voltage at the output of the voltage pump based on the series of pump stages and the second voltage. ### Claim 19 (depends on 14) The system of claim 14, wherein the interface further comprises a third voltage pin configured to receive a third voltage, wherein the memory device further comprises a second voltage detector coupled to the voltage pin and configured to detect a value of the third voltage received at the third voltage pin, and wherein the control circuit is configured to: receive the value of the third voltage from the second voltage detector, determine whether the value of the third voltage matches a predetermined voltage associated with the target voltage, and in response to determining that the value of the third voltage fails to match the predetermined voltage, disable receiving the third voltage at the third voltage pin and control the pump switch circuit to be coupled to the corresponding node in the voltage pump based on the value of the input voltage to generate the target voltage. ### Claim 20 (depends on 11) The system of claim 11, wherein the interface comprises a plurality of additional voltage pins including the voltage pin, and wherein the memory device comprises a plurality of voltage pumps, and wherein each of the plurality of additional voltage pins is coupled to a corresponding voltage pump of the plurality of voltage pumps. ### Claim 21 (depends on 11) The system of claim 11, further comprising: a row decoder coupled to the memory array and configured to select each of the plurality of word lines; and a switch circuit coupled between the row decoder and the voltage generator, wherein the switch circuit is configured to: generate a set of operation voltages based on the target voltage, and output the set of operation voltages to the row decoder, and wherein the row decoder is configured to apply the set of operation voltages respectively to corresponding word lines of the plurality of word lines, and wherein the memory device is configured to perform the operation based on the set of operation voltages to the corresponding word lines. ### Claim 22 A method performed by a semiconductor device, the method comprising: receiving a command to perform an operation in the semiconductor device; receiving a signal indicating a target voltage associated with the operation; detecting a value of an input voltage at a voltage pin of the semiconductor device, wherein the semiconductor device comprises a pump switch circuit coupled to the voltage pin; controlling the pump switch circuit to be coupled to a corresponding node in a voltage pump of the semiconductor device based on the value of the input voltage and the signal indicating the target voltage, wherein the voltage pump comprises an input, an output, and a series of pump stages coupled between the input and the output; generating the target voltage at the output of the voltage pump using a corresponding number of pump stages coupled between the corresponding node and the output; and performing the operation based on the target voltage. ### Claim 23 (depends on 22) The method of claim 22, further comprising: receiving a second input voltage from a second voltage pin; determining whether the second input voltage matches a predetermined voltage that is associated with the target voltage; and in response to determining that the second input voltage fails to match the predetermined voltage, disabling receiving the second input voltage to the semiconductor device, wherein controlling the pump switch circuit to be coupled to the corresponding node in the voltage pump is in response to determining that the second input voltage fails to match the predetermined voltage.