# US 2025/0095740 A1 · Non-volatile memory with efficient precharge in sub-block mode

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- Number: US 2025/0095740 A1
- Document ID: US20250095740A1
- Status: Published application
- Kind: A1
- Application number: 18/468,349
- Filed: 2023-09-15
- Published: 2025-03-20
- Earliest claimed: 2023-09-15
- Assignees: Western Digital Technologies, Inc.
- Applicants: Western Digital Technologies, Inc.
- Inventors: Wei Cao; Dengtao Zhao; Peng Zhang; Xiang Yang
- Web page: https://patentgrep.com/patent/US20250095740A1

## CPC

- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/10: Programming or data input circuits
- G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written}
- H10W 90/00: Package configurations
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A block of non-volatile memory cells is divided into a first sub-block and a second sub-block. Programming non-volatile memory cells of the second sub-block after programming non-volatile memory cells of the first sub-block comprises boosting unselected channels in the second sub-block to a boosted condition; prior to boosting unselected channels in the second sub-block to the boosted condition, boosting unselected channels in the first sub-block to the boosted condition to pre-charge the channels of the second sub-block; and applying a program voltage to a selected word line of the second sub-block while channels in the first sub-block are in the boosted condition and channels in the first sub-block are in the boosted condition.

## Claims

### Claim 1

A non-volatile storage apparatus, comprising:
non-volatile memory cells organized into groups of memory cells, the groups of memory cells form a block, the block is divided into a first sub-block and a second sub-block, the non-volatile memory cells include channels; and
a control circuit connected to the non-volatile memory cells, the control circuit is configured to:
boost unselected channels in the second sub-block to a boosted condition, the boosted condition prevents unselected memory cells from experiencing unwanted programming;
prior to boosting unselected channels in the second sub-block to the boosted condition, boost unselected channels in the first sub-block to the boosted condition to pre-charge the channels of the second sub-block; and
applying a program voltage to a selected word line of the second sub-block while channels in the first sub-block are in the boosted condition and channels in the first sub-block are in the boosted condition.

### Claim 2 (depends on 1)

The non-volatile storage apparatus of claim 1, wherein:
the control circuit is configured to isolate unselected channels in the second sub-block from unselected channels in the first sub-block after boosting the unselected channels in the first sub-block and before boosting unselected channels in the second sub-block.

### Claim 3 (depends on 1)

The non-volatile storage apparatus of claim 1, further comprising:
data word lines connected to the groups of memory cells, including a first set of data word lines connected to non-volatile memory cells in the first sub-block and a second set of data word lines connected to non-volatile memory cells in the second sub-block; and
a dummy word line connected to the groups of memory cells, the dummy word line is positioned between the first sub-block and the second sub-block, the control circuit is configured to adjust voltage applied to the dummy word line to isolate the first sub-block from the second sub-block after boosting the unselected channels in the first sub-block and before boosting unselected channels in the second sub-block.

### Claim 4 (depends on 1)

The non-volatile storage apparatus of claim 1, wherein:
the control circuit is configured to program non-volatile memory cells of the first sub-block in a same word line direction of as programming non-volatile memory cells of the second sub-block.

### Claim 5 (depends on 1)

The non-volatile storage apparatus of claim 1, wherein:
the control circuit is configured to program non-volatile memory cells of the first sub-block and non-volatile memory cells of the second sub-block in a word line direction from the second sub-block toward the first sub-block.

### Claim 6 (depends on 1)

The non-volatile storage apparatus of claim 1, further comprising:
a first selection line connected to a first side of the groups of memory cells, the first sub-block is positioned between the first selection line and the second sub-block; and
a second selection line connected to a second side of the groups of memory cells opposite the first side of the groups of memory cells, the second sub-block is positioned between the second selection line and the first sub-block, the control circuit is configured to program non-volatile memory cells of the first sub-block and the second sub-block in a word line direction from second control line toward the first control line.

### Claim 7 (depends on 1)

The non-volatile storage apparatus of claim 1, wherein:
the control circuit is configured to pre-charge the unselected channels of the first sub-block prior to the boosting the unselected channels in the first sub-block.

### Claim 8 (depends on 1)

The non-volatile storage apparatus of claim 1, wherein:
the control circuit is configured to not pre-charge the unselected channels of the first sub-block prior to the boosting the unselected channels in the first sub-block.

### Claim 9 (depends on 1)

The non-volatile storage apparatus of claim 1, wherein:
the control circuit is configured to isolate unselected channels in the second sub-block from unselected channels in the first sub-block after boosting the unselected channels in the first sub-block and before boosting unselected channels in the second sub-block; and
the control circuit is configured to pre-charge the unselected channels of the first sub-block prior to the boosting the unselected channels in the first sub-block such that stray electrons remain in the unselected channels in the second sub-block, the boosting of the unselected channels in the first sub-block to the boosted condition to pre-charge the channels of the second sub-block removes the stray electrons from the unselected channels in the second sub-block, the isolating unselected channels in the second sub-block from unselected channels in the first sub-block inhibits electrons from moving from unselected channels in the first sub-block to unselected channels in the second sub-block.

### Claim 10 (depends on 1)

The non-volatile storage apparatus of claim 1, further comprising:
data word lines connected to the groups of memory cells including a first set of data word lines connected to non-volatile memory cells in the first sub-block and a second set of data word lines connected to non-volatile memory cells in the second sub-block, the control circuit is configured to boost unselected channels in the second sub-block to the boosted condition by ramping up data word lines of the second sub-block, the control circuit is configured to boost unselected channels in the first sub-block to the boosted condition by ramping up data word lines of the first sub-block.

### Claim 11 (depends on 10)

The non-volatile storage apparatus of claim 10, further comprising:
dummy word lines connected to the groups of memory cells, the dummy word lines are positioned between the first sub-block and the second sub-block, the control circuit is configured to adjust voltage applied to the dummy word lines to isolate the first sub-block from the second sub-block after boosting the unselected channels in the first sub-block and before boosting unselected channels in the second sub-block.

### Claim 12 (depends on 1)

The non-volatile storage apparatus of claim 1, wherein:
the control circuit is configured to:
program the first sub-block independent from programming the second sub-block,
program the second sub-block independent from programming the first sub-block, and
program the first sub-block prior to programming the second sub-block such that the boosting unselected channels in the second sub-block and the boosting unselected channels in the first sub-block is performed to program the second sub-block after programming the first sub-block.

### Claim 13 (depends on 1)

The non-volatile storage apparatus of claim 1, wherein:
the non-volatile memory cells are arranged as NAND strings, each NAND string includes some non-volatile memory cells in the first sub-block and some non-volatile memory cells in the second sub-block.

### Claim 14 (depends on 13)

The non-volatile storage apparatus of claim 13, further comprising:
a plurality of data word lines connected to the NAND strings, a first subset of the data word lines are connected to memory cells of the first sub-block, a second subset of the data word lines are connected to memory cells of the second sub-block, the control circuit is connected to the data word lines;
dummy word lines connected to the groups of memory cells, the dummy word lines are positioned between the first sub-block and the second sub-block, the control circuit is configured to adjust voltage applied to the dummy word lines to isolate the first sub-block from the second sub-block after boosting the unselected channels in the first sub-block and before boosting unselected channels in the second sub-block, the control circuit is connected to the dummy word lines;
a first selection line connected to a first side of the NAND strings, the first sub-block is positioned between the first selection line and the second sub-block;
a second selection line connected to a second side of the NAND strings opposite the first side of the NAND strings, the second sub-block is positioned between the second selection line and the first sub-block, the control circuit is connected to the first selection line and the second selection line;
the control circuit is configured to program non-volatile memory cells of the first sub-block and the second sub-block in a word line direction from second control line toward the first control line;
the control circuit is configured to boost unselected channels in the second sub-block to the boosted condition by boosting channels of unselected NAND strings in the second sub-block to cause channels of the unselected NAND strings in the second sub-block to increase to a voltage that inhibits programming for memory cells of the unselected NAND strings in the second sub-block that are connected to a selected data word line;
the control circuit is configured to boost unselected channels in the first sub-block to the boosted condition by boosting channels of unselected NAND strings in the first sub-block to cause channels of the unselected NAND strings in the first sub-block to increase to a voltage that inhibits programming for memory cells of the unselected NAND strings in the first sub-block that are connected to the selected data word line and to cause channels of the unselected NAND strings in the second sub-block to pre-charge prior to the boosting channels of the unselected NAND strings in the second sub-block.

### Claim 15

A method of programming memory cells that are positioned in a block, the block is divided into a first sub-block and a second sub-block, comprising:
ramping up data word lines of the second sub-block to boost channels in the second sub-block to a boosted condition;
prior to ramping up data word lines of the second sub-block, ramping up data word lines of the first sub-block to boost channels in the first sub-block to the boosted condition and to pre-charge the channels of the second sub-block; and
applying a program voltage to a selected word line of the second sub-block while channels in the first sub-block are boosted and channels in the first sub-block are in the boosted condition.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
isolating channels in the second sub-block from channels in the first sub-block after ramping up data word lines of the first sub-block and before ramping up data word lines of the second sub-block.

### Claim 17 (depends on 15)

The method of claim 15, further comprising:
ramping down a dummy word line positioned between the first sub-block and the second sub-block after ramping up data word lines of the first sub-block and before ramping up data word lines of the second sub-block to isolate channels in the second sub-block from channels in the first sub-block.

### Claim 18 (depends on 15)

The method of claim 15, further comprising:
programming memory cells of the first sub-block in a word line direction from the second sub-block toward the first sub-block; and
programming memory cells of the second sub-block in a word line direction from the second sub-block toward the first sub-block.

### Claim 19 (depends on 15)

The method of claim 15, further comprising:
programming memory cells of the first sub-block in a word line direction from a second control line toward a first control line, the first selection line connected to a first side of the block, the first sub-block is positioned between the first selection line and the second sub-block, the second selection line is connected to a second side of the block opposite the first side, the second sub-block is positioned between the second selection line and the first sub-block; and
programming memory cells of the second sub-block in a word line direction from the second control line toward the first control line.

### Claim 20

A non-volatile storage apparatus, comprising:
a plurality of NAND strings arranged as a block of non-volatile memory cells, the block is divided into a first sub-block and a second sub-block such that each NAND string includes some non-volatile memory cells in the first sub-block and some non-volatile memory cells in the second sub-block;
a plurality of bit lines connected to the NAND strings such that each bit line is connected to non-volatile memory cells of the first sub-block and to non-volatile memory cells of the second sub-block;
a plurality of data word lines connected to the NAND strings, a first subset of the data word lines are connected to memory cells of the first sub-block, a second subset of the data word lines are connected to memory cells of the second sub-block;
a first selection line connected to a first side of the NAND strings, the first sub-block is positioned between the first selection line and the second sub-block;
a second selection line connected to a second side of the NAND strings opposite the first side of the NAND strings, the second sub-block is positioned between the second selection line and the first sub-block; and
a control circuit connected to the data word lines, the first selection line, the second selection line and the bit lines;
the control circuit is configured to program non-volatile memory cells of the first sub-block and the second sub-block in a word line direction from second control line toward the first control line, the control circuit is configured to program non-volatile memory cells of the second sub-block by:
boosting channels of unselected NAND strings in the second sub-block to cause channels of the unselected NAND strings in the second sub-block to increase to a voltage that inhibits programming for memory cells of the unselected NAND strings in the second sub-block and that are connected to a selected data word line,
prior to the boosting channels of unselected NAND strings in the second sub-block, boosting channels of unselected NAND strings in the first sub-block to cause channels of the unselected NAND strings in the first sub-block to increase to a voltage that inhibits programming for memory cells of the unselected NAND strings in the first sub-block and that are connected to the selected data word line and to cause channels of the unselected NAND strings in the second sub-block to pre-charge prior to the boosting channels of the unselected NAND strings in the second sub-block, and
apply a program voltage to the selected data word line.